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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 03:02:45 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 03:02:45 +0800 |
| commit | 888e9b5bb57a79f4eee88a7926cb859e04823361 (patch) | |
| tree | 58cba25d087e43862ba7de139b49e126f6d7445c /backend/lib/Target/RISCV/RISCVMCCodeEmitter.cpp | |
| parent | 23dad063b9172982467b69650ae334bbec63e759 (diff) | |
| download | rcc-project-888e9b5bb57a79f4eee88a7926cb859e04823361.tar.gz rcc-project-888e9b5bb57a79f4eee88a7926cb859e04823361.tar.xz | |
[RISCV] Add Zba and Zbb instruction descriptions
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVMCCodeEmitter.cpp')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVMCCodeEmitter.cpp | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/backend/lib/Target/RISCV/RISCVMCCodeEmitter.cpp b/backend/lib/Target/RISCV/RISCVMCCodeEmitter.cpp index 81ac0f1..9ba3021 100644 --- a/backend/lib/Target/RISCV/RISCVMCCodeEmitter.cpp +++ b/backend/lib/Target/RISCV/RISCVMCCodeEmitter.cpp @@ -270,6 +270,7 @@ namespace { break; case AssemblyFormat::RD_FRS1: case AssemblyFormat::FRD_RS1: + case AssemblyFormat::RD_RS1: RegisterCount = 2; break; default: @@ -358,6 +359,18 @@ namespace { static_cast<std::uint32_t>(*Predecessor) << 24U | static_cast<std::uint32_t>(*Successor) << 20U; } + if (Format == AssemblyFormat::RD_RS1) { + auto Count = requireOperandCount(Instruction, 2); + if (!Count) + return std::unexpected(Count.error()); + auto Destination = registerEncoding(Instruction, 0, Target); + auto Source = registerEncoding(Instruction, 1, Target); + if (!Destination) + return std::unexpected(Destination.error()); + if (!Source) + return std::unexpected(Source.error()); + return (Assembly.Encoding & ~std::uint32_t{0x000f8f80}) | *Destination << 7U | *Source << 15U; + } if (Format != AssemblyFormat::RD_RS1_IMM && Format != AssemblyFormat::RD_OFFSET_RS1 && Format != AssemblyFormat::FRD_OFFSET_RS1) { return makeUnexpected(ErrorCode::InstructionEncodingFailed, @@ -376,8 +389,8 @@ namespace { (Assembly.Encoding & ~std::uint32_t{0x000f8f80}) | *Destination << 7U | *Source << 15U; const auto Opcode = static_cast<InstructionOpcode>(Instruction.opcode().value()); - const bool Shift64 = Opcode == InstructionOpcode::SLLI || Opcode == InstructionOpcode::SRLI || - Opcode == InstructionOpcode::SRAI; + const bool Shift64 = Opcode == InstructionOpcode::SLLI || Opcode == InstructionOpcode::SLLI_UW || + Opcode == InstructionOpcode::SRLI || Opcode == InstructionOpcode::SRAI; const bool Shift32 = Opcode == InstructionOpcode::SLLIW || Opcode == InstructionOpcode::SRLIW || Opcode == InstructionOpcode::SRAIW; if (Shift64 || Shift32) { |