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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-24 17:30:29 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-24 17:30:29 +0800 |
| commit | 81afb6570000472c182e5b1f540f69382602aaad (patch) | |
| tree | 4fdab5a642e5088cd456662d438e96d195fdc3d4 /backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc | |
| parent | 47d0d5140b4616ae4dd7c6d2c3c089ccbfc3b009 (diff) | |
| download | rcc-project-81afb6570000472c182e5b1f540f69382602aaad.tar.gz rcc-project-81afb6570000472c182e5b1f540f69382602aaad.tar.xz | |
[RISCV] Match LLVM emergency spill layout
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc index a2f26dc..9e5a237 100644 --- a/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc +++ b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc @@ -247,7 +247,7 @@ register_classes: spill_alignment_bits: 64 lanes: 1 registers: [X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] - allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] + allocation_order: [X10, X11, X12, X13, X14, X15, X16, X17, X5, X6, X7, X28, X29, X30, X31, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] - id: 2 symbol: GPRC @@ -317,7 +317,7 @@ register_classes: spill_alignment_bits: 64 lanes: 1 registers: [X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] - allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] + allocation_order: [X10, X11, X12, X13, X14, X15, X16, X17, X5, X6, X7, X28, X29, X30, X31, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] - id: 8 symbol: GPR_NX0_NX2 @@ -329,7 +329,7 @@ register_classes: spill_alignment_bits: 64 lanes: 1 registers: [X1, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] - allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] + allocation_order: [X10, X11, X12, X13, X14, X15, X16, X17, X5, X6, X7, X28, X29, X30, X31, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] - id: 9 symbol: FFLAGS @@ -377,7 +377,7 @@ register_classes: spill_alignment_bits: 64 lanes: 1 registers: [X6, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] - allocation_order: [X6, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27] + allocation_order: [X10, X11, X12, X13, X14, X15, X16, X17, X6, X28, X29, X30, X31, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27] register_masks: - |