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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-25 02:38:56 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-25 02:38:56 +0800 |
| commit | c3932f55208e3fe2019d26a0e5af421c0b644872 (patch) | |
| tree | ba4fee68834007bd8cd1ce0f209d8c1deb5dd530 /backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc | |
| parent | 71988f9818677df0d90b19d4bb770ac8a6116e62 (diff) | |
| download | rcc-project-c3932f55208e3fe2019d26a0e5af421c0b644872.tar.gz rcc-project-c3932f55208e3fe2019d26a0e5af421c0b644872.tar.xz | |
[RISCV] Implement make-compressible pass
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc index 4806ec4..975aa56 100644 --- a/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc +++ b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc @@ -270,7 +270,7 @@ register_classes: spill_alignment_bits: 64 lanes: 1 registers: [F0_D, F1_D, F2_D, F3_D, F4_D, F5_D, F6_D, F7_D, F8_D, F9_D, F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D, F28_D, F29_D, F30_D, F31_D] - allocation_order: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D, F0_D, F1_D, F2_D, F3_D, F4_D, F5_D, F6_D, F7_D, F28_D, F29_D, F30_D, F31_D, F8_D, F9_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D] + allocation_order: [F15_D, F14_D, F13_D, F12_D, F11_D, F10_D, F0_D, F1_D, F2_D, F3_D, F4_D, F5_D, F6_D, F7_D, F16_D, F17_D, F28_D, F29_D, F30_D, F31_D, F8_D, F9_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D] - id: 4 symbol: FPR64C @@ -282,7 +282,7 @@ register_classes: spill_alignment_bits: 64 lanes: 1 registers: [F8_D, F9_D, F10_D, F11_D, F12_D, F13_D, F14_D, F15_D] - allocation_order: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F8_D, F9_D] + allocation_order: [F15_D, F14_D, F13_D, F12_D, F11_D, F10_D, F8_D, F9_D] - id: 5 symbol: FPR32 @@ -293,7 +293,7 @@ register_classes: spill_alignment_bits: 32 lanes: 1 registers: [F0_F, F1_F, F2_F, F3_F, F4_F, F5_F, F6_F, F7_F, F8_F, F9_F, F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F16_F, F17_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F, F28_F, F29_F, F30_F, F31_F] - allocation_order: [F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F16_F, F17_F, F0_F, F1_F, F2_F, F3_F, F4_F, F5_F, F6_F, F7_F, F28_F, F29_F, F30_F, F31_F, F8_F, F9_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F] + allocation_order: [F15_F, F14_F, F13_F, F12_F, F11_F, F10_F, F0_F, F1_F, F2_F, F3_F, F4_F, F5_F, F6_F, F7_F, F16_F, F17_F, F28_F, F29_F, F30_F, F31_F, F8_F, F9_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F] - id: 6 symbol: FPR32C @@ -305,7 +305,7 @@ register_classes: spill_alignment_bits: 32 lanes: 1 registers: [F8_F, F9_F, F10_F, F11_F, F12_F, F13_F, F14_F, F15_F] - allocation_order: [F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F8_F, F9_F] + allocation_order: [F15_F, F14_F, F13_F, F12_F, F11_F, F10_F, F8_F, F9_F] - id: 7 symbol: GPR_NX0 |