[RISCV] Consolidate instruction behavior in RISCVInstrInfo

6 files changed, 140 insertions, 214 deletions

diff --git a/backend/lib/Target/RISCV/CMakeLists.txt b/backend/lib/Target/RISCV/CMakeLists.txt
index 68bd444..d28cdf3 100644
--- a/backend/lib/Target/RISCV/CMakeLists.txt
+++ b/backend/lib/Target/RISCV/CMakeLists.txt
@@ -47,7 +47,7 @@ set_source_files_properties(
 
 add_library(
   RCCBackendRISCV
-  RISCVBranchInfo.cpp
+  RISCVInstrInfo.cpp
   RISCVCodeGen.cpp
   RISCVCallLowering.cpp
   RISCVAssemblyPrinter.cpp
@@ -84,7 +84,9 @@ target_include_directories(
     "$<BUILD_INTERFACE:${RCC_BACKEND_SOURCE_DIR}/include>"
     "$<BUILD_INTERFACE:${RCC_BACKEND_BINARY_DIR}/generated/include>"
     "$<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>"
-  PRIVATE "${RCC_BACKEND_BINARY_DIR}/generated/lib/Target/RISCV"
+  PRIVATE
+    "${CMAKE_CURRENT_SOURCE_DIR}"
+    "${RCC_BACKEND_BINARY_DIR}/generated/lib/Target/RISCV"
 )
 target_link_libraries(
   RCCBackendRISCV
@@ -116,7 +118,7 @@ install(
 )
 
 rcc_backend_register_format_files(
-  "${CMAKE_CURRENT_SOURCE_DIR}/RISCVBranchInfo.cpp"
+  "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfo.cpp"
   "${CMAKE_CURRENT_SOURCE_DIR}/RISCVAssemblyPrinter.cpp"
   "${CMAKE_CURRENT_SOURCE_DIR}/RISCVCodeGen.cpp"
   "${CMAKE_CURRENT_SOURCE_DIR}/RISCVCallLowering.cpp"
@@ -140,6 +142,7 @@ rcc_backend_register_format_files(
   "${CMAKE_CURRENT_SOURCE_DIR}/RISCVTarget.cpp"
   "${CMAKE_CURRENT_SOURCE_DIR}/RISCVTargetConstant.cpp"
   "${RCC_BACKEND_SOURCE_DIR}/include/rcc/Target/RISCV/RISCVCodeGen.h"
+  "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfo.h"
   "${RCC_BACKEND_SOURCE_DIR}/include/rcc/Target/RISCV/RISCVAssemblyPrinter.h"
   "${RCC_BACKEND_SOURCE_DIR}/include/rcc/Target/RISCV/RISCVCallLowering.h"
   "${RCC_BACKEND_SOURCE_DIR}/include/rcc/Target/RISCV/RISCVInstPrinter.h"
@@ -156,7 +159,7 @@ rcc_backend_register_format_files(
   "${RCC_BACKEND_SOURCE_DIR}/include/rcc/Target/RISCV/RISCVTargetRelocationKinds.h"
 )
 rcc_backend_register_tidy_files(
-  "${CMAKE_CURRENT_SOURCE_DIR}/RISCVBranchInfo.cpp"
+  "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfo.cpp"
   "${CMAKE_CURRENT_SOURCE_DIR}/RISCVAssemblyPrinter.cpp"
   "${CMAKE_CURRENT_SOURCE_DIR}/RISCVCodeGen.cpp"
   "${CMAKE_CURRENT_SOURCE_DIR}/RISCVCallLowering.cpp"
diff --git a/backend/lib/Target/RISCV/RISCVCodeGen.cpp b/backend/lib/Target/RISCV/RISCVCodeGen.cpp
index d03653f..00dba94 100644
--- a/backend/lib/Target/RISCV/RISCVCodeGen.cpp
+++ b/backend/lib/Target/RISCV/RISCVCodeGen.cpp
@@ -6512,198 +6512,6 @@ private:
   }
 };
 
-class RISCVSSAInfo final : public TargetSSAInfo {
-public:
-  [[nodiscard]] Expected<bool> isFallthroughEdge(const MachineBasicBlock &From,
-                                                 const MachineBasicBlock &To,
-                                                 const MachineFunction &,
-                                                 const TargetDescription &Target) const override {
-    if (From.next() != &To ||
-        std::ranges::none_of(From.successors(), [&To](const MachineSuccessor &Successor) {
-          return Successor.Block == &To;
-        })) {
-      return false;
-    }
-
-    bool CanFallThrough = true;
-    for (const MachineInstr *Instruction = From.firstInstruction(); Instruction != nullptr;
-         Instruction = Instruction->next()) {
-      const InstructionDescriptor *Descriptor = Target.instructionDescriptor(Instruction->opcode());
-      if (Descriptor == nullptr) {
-        return makeUnexpected(ErrorCode::VerificationError,
-                              "RISC-V fallthrough analysis encountered an unknown opcode");
-      }
-      if (!Descriptor->Flags.has(InstructionFlag::Terminator))
-        continue;
-      CanFallThrough = isConditionalBranch(Instruction->opcode());
-    }
-    return CanFallThrough;
-  }
-
-  [[nodiscard]] Expected<bool> rewriteBranchTarget(MachineBasicBlock &Block,
-                                                   MachineBasicBlock &OldTarget,
-                                                   MachineBasicBlock &NewTarget,
-                                                   MachineFunction &Function,
-                                                   const TargetDescription &Target) const override {
-    if (&Block.function() != &Function || &OldTarget.function() != &Function ||
-        &NewTarget.function() != &Function) {
-      return makeUnexpected(ErrorCode::InvalidArgument,
-                            "RISC-V branch rewrite references another machine function");
-    }
-
-    bool Changed = false;
-    for (MachineInstr *Instruction = Block.firstInstruction(); Instruction != nullptr;
-         Instruction = Instruction->next()) {
-      const InstructionDescriptor *Descriptor = Target.instructionDescriptor(Instruction->opcode());
-      if (Descriptor == nullptr) {
-        return makeUnexpected(ErrorCode::VerificationError,
-                              "RISC-V branch rewrite encountered an unknown opcode");
-      }
-      if (!Descriptor->Flags.has(InstructionFlag::Branch) ||
-          Descriptor->Flags.has(InstructionFlag::IndirectBranch)) {
-        continue;
-      }
-      for (std::size_t Index = 0; Index < Instruction->operandCount(); ++Index) {
-        MachineOperand *Operand = Instruction->operandAt(Index);
-        const BasicBlockOperand *TargetOperand =
-            Operand == nullptr ? nullptr : Operand->getIf<BasicBlockOperand>();
-        if (TargetOperand == nullptr || TargetOperand->Block != &OldTarget)
-          continue;
-        auto Rewritten = Operand->setBasicBlock(NewTarget);
-        if (!Rewritten)
-          return std::unexpected(Rewritten.error());
-        Changed = true;
-      }
-    }
-    return Changed;
-  }
-
-  [[nodiscard]] Expected<void>
-  insertUnconditionalBranch(MachineBasicBlock &Block, MachineBasicBlock &TargetBlock,
-                            MachineFunction &Function,
-                            const TargetDescription &Target) const override {
-    if (&Block.function() != &Function || &TargetBlock.function() != &Function) {
-      return makeUnexpected(ErrorCode::InvalidArgument,
-                            "RISC-V branch insertion references another machine function");
-    }
-    auto Zero = physicalRegister(PhysicalRegisterID::X0);
-    if (!Zero)
-      return std::unexpected(Zero.error());
-    MachineIRBuilder Builder(Function, Target);
-    auto Point = Builder.setInsertPoint(Block);
-    if (!Point)
-      return std::unexpected(Point.error());
-    auto Branch = Builder.buildInstr(targetOpcode(InstructionOpcode::JAL));
-    if (!Branch)
-      return std::unexpected(Branch.error());
-    auto Link = Branch->addDef(Register::fromPhysical(*Zero));
-    if (!Link)
-      return std::unexpected(Link.error());
-    auto Destination = Branch->addBasicBlock(TargetBlock);
-    if (!Destination)
-      return std::unexpected(Destination.error());
-    auto Built = Branch->build();
-    if (!Built)
-      return std::unexpected(Built.error());
-    return {};
-  }
-
-  [[nodiscard]] Expected<void> validateCopy(Register Destination, SubRegIndex DestinationSubReg,
-                                            Register Source, SubRegIndex SourceSubReg,
-                                            const MachineFunction &Function,
-                                            const TargetDescription &Target) const override {
-    if (Destination.isNoRegister() || Source.isNoRegister()) {
-      return makeUnexpected(ErrorCode::VerificationError,
-                            "RISC-V COPY requires two nonzero registers");
-    }
-    if (DestinationSubReg.value() != 0 || SourceSubReg.value() != 0) {
-      return makeUnexpected(ErrorCode::Unsupported, "RV64GC does not model register subindices");
-    }
-
-    auto DestinationShape = copyShape(Destination, Function, Target);
-    if (!DestinationShape)
-      return std::unexpected(DestinationShape.error());
-    auto SourceShape = copyShape(Source, Function, Target);
-    if (!SourceShape)
-      return std::unexpected(SourceShape.error());
-    if (DestinationShape->Bank == SourceShape->Bank) {
-      if (DestinationShape->Width && SourceShape->Width &&
-          DestinationShape->Width != SourceShape->Width) {
-        return makeUnexpected(ErrorCode::Unsupported,
-                              "RISC-V same-bank COPY has incompatible register widths");
-      }
-      return {};
-    }
-
-    const RegisterBankID GPR =
-        RegisterBankID::fromValue(static_cast<std::uint32_t>(RegisterBank::GPR));
-    const RegisterBankID FPR =
-        RegisterBankID::fromValue(static_cast<std::uint32_t>(RegisterBank::FPR));
-    const bool IsCrossBankMove = (DestinationShape->Bank == GPR && SourceShape->Bank == FPR) ||
-                                 (DestinationShape->Bank == FPR && SourceShape->Bank == GPR);
-    if (!IsCrossBankMove) {
-      return makeUnexpected(ErrorCode::Unsupported,
-                            "RISC-V COPY crosses unsupported register banks");
-    }
-    auto SupportedWidth = [](std::optional<std::uint32_t> Width) {
-      return !Width || *Width == 32 || *Width == 64;
-    };
-    if (!SupportedWidth(DestinationShape->Width) || !SupportedWidth(SourceShape->Width)) {
-      return makeUnexpected(ErrorCode::Unsupported,
-                            "RISC-V GPR/FPR COPY requires 32-bit or 64-bit values");
-    }
-    return {};
-  }
-
-private:
-  struct CopyShape final {
-    RegisterBankID Bank;
-    std::optional<std::uint32_t> Width;
-  };
-
-  [[nodiscard]] static bool isConditionalBranch(Opcode Value) noexcept {
-    return Value == targetOpcode(InstructionOpcode::BEQ) ||
-           Value == targetOpcode(InstructionOpcode::BNE) ||
-           Value == targetOpcode(InstructionOpcode::BLT) ||
-           Value == targetOpcode(InstructionOpcode::BGE) ||
-           Value == targetOpcode(InstructionOpcode::BLTU) ||
-           Value == targetOpcode(InstructionOpcode::BGEU);
-  }
-
-  [[nodiscard]] static Expected<CopyShape> copyShape(Register Reg, const MachineFunction &Function,
-                                                     const TargetDescription &Target) {
-    if (Reg.isVirtual()) {
-      auto Info = Function.registerInfo().virtualRegisterInfo(Reg);
-      if (!Info)
-        return std::unexpected(Info.error());
-      const std::optional<RegisterBankID> &Bank = Info->get().Bank;
-      const std::optional<RegisterClassID> &RegClass = Info->get().RegClass;
-      if (!Bank || !RegClass) {
-        return makeUnexpected(ErrorCode::VerificationError,
-                              "RISC-V COPY virtual register is not fully constrained");
-      }
-      const RegisterClassDesc *Class = Target.registers().registerClass(RegClass.value());
-      if (Class == nullptr) {
-        return makeUnexpected(ErrorCode::VerificationError,
-                              "RISC-V COPY references an unknown register class");
-      }
-      return CopyShape{Bank.value(), Class->SizeInBits};
-    }
-
-    const std::optional<PhysicalRegister> Physical = Reg.physicalRegister();
-    if (!Physical || !Target.registers().isKnownPhysicalRegister(*Physical)) {
-      return makeUnexpected(ErrorCode::VerificationError,
-                            "RISC-V COPY references an unknown physical register");
-    }
-    for (const RegisterBankDesc &Bank : Target.registers().registerBanks()) {
-      if (Target.registers().bankContainsRegister(Bank.ID, *Physical))
-        return CopyShape{Bank.ID, std::nullopt};
-    }
-    return makeUnexpected(ErrorCode::VerificationError,
-                          "RISC-V physical register is not assigned to a register bank");
-  }
-};
-
 } // namespace
 
 const TargetLegalizerInfo &legalizerInfo() noexcept {
@@ -6725,9 +6533,4 @@ const TargetInstructionSelector &instructionSelector() noexcept {
   return Value;
 }
 
-const TargetSSAInfo &ssaInfo() noexcept {
-  static const RISCVSSAInfo Value;
-  return Value;
-}
-
 } // namespace rcc::riscv
diff --git a/backend/lib/Target/RISCV/RISCVBranchInfo.cpp b/backend/lib/Target/RISCV/RISCVInstrInfo.cpp
index 059bbef..6e26e2c 100644
--- a/backend/lib/Target/RISCV/RISCVBranchInfo.cpp
+++ b/backend/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-3.0-or-later
 
+#include "RISCVInstrInfo.h"
+
 #include "rcc/CodeGen/InstructionDescriptor.h"
 #include "rcc/CodeGen/MachineBasicBlock.h"
 #include "rcc/CodeGen/MachineFunction.h"
@@ -8,7 +10,6 @@
 #include "rcc/CodeGen/MachineOperand.h"
 #include "rcc/CodeGen/MachineRegisterInfo.h"
 #include "rcc/CodeGen/TargetDescription.h"
-#include "rcc/Target/RISCV/RISCVCodeGen.h"
 #include "rcc/Target/RISCV/RISCVInstructions.h"
 #include "rcc/Target/RISCV/RISCVRegisters.h"
 #include "rcc/Target/RISCV/RISCVTarget.h"
@@ -497,7 +498,7 @@ selectLongBranchScratch(const MachineInstr &Instruction, const MachineBasicBlock
   return true;
 }
 
-class RISCVBranchInfo final : public TargetInstrInfo {
+class RISCVInstrInfo final : public TargetInstrInfo {
 public:
   [[nodiscard]] Expected<MachineBranchAnalysis>
   analyzeBranch(MachineBasicBlock &Block, MachineFunction &Function,
@@ -623,9 +624,8 @@ public:
   }
 
   [[nodiscard]] Expected<MachineInstr *>
-  insertUnconditionalBranch(MachineBasicBlock &Block, MachineBasicBlock &TargetBlock,
-                            MachineFunction &Function,
-                            const TargetDescription &Target) const override {
+  insertBranch(MachineBasicBlock &Block, MachineBasicBlock &TargetBlock, MachineFunction &Function,
+               const TargetDescription &Target) const override {
     if (&Block.function() != &Function || &TargetBlock.function() != &Function)
       return makeUnexpected(ErrorCode::InvalidArgument,
                             "RISC-V branch insertion references another function");
@@ -635,6 +635,75 @@ public:
     return buildJAL(Function, Target, Block, nullptr, *Zero, TargetBlock);
   }
 
+  [[nodiscard]] Expected<bool> isFallthroughEdge(const MachineBasicBlock &From,
+                                                 const MachineBasicBlock &To,
+                                                 const MachineFunction &Function,
+                                                 const TargetDescription &Target) const override {
+    if (&From.function() != &Function || &To.function() != &Function)
+      return makeUnexpected(ErrorCode::InvalidArgument,
+                            "RISC-V fallthrough query references another machine function");
+    if (From.next() != &To ||
+        std::ranges::none_of(From.successors(), [&To](const MachineSuccessor &Successor) {
+          return Successor.Block == &To;
+        })) {
+      return false;
+    }
+
+    bool CanFallThrough = true;
+    for (const MachineInstr *Instruction = From.firstInstruction(); Instruction != nullptr;
+         Instruction = Instruction->next()) {
+      const InstructionDescriptor *Descriptor = Target.instructionDescriptor(Instruction->opcode());
+      if (Descriptor == nullptr)
+        return makeUnexpected(ErrorCode::VerificationError,
+                              "RISC-V fallthrough analysis encountered an unknown opcode");
+      if (Descriptor->Flags.has(InstructionFlag::Terminator))
+        CanFallThrough = isConditionalBranch(Instruction->opcode());
+    }
+    return CanFallThrough;
+  }
+
+  [[nodiscard]] Expected<void> validateCopy(Register Destination, SubRegIndex DestinationSubReg,
+                                            Register Source, SubRegIndex SourceSubReg,
+                                            const MachineFunction &Function,
+                                            const TargetDescription &Target) const override {
+    if (Destination.isNoRegister() || Source.isNoRegister())
+      return makeUnexpected(ErrorCode::VerificationError,
+                            "RISC-V COPY requires two nonzero registers");
+    if (DestinationSubReg.value() != 0 || SourceSubReg.value() != 0)
+      return makeUnexpected(ErrorCode::Unsupported, "RV64GC does not model register subindices");
+
+    auto DestinationShape = copyShape(Destination, Function, Target);
+    if (!DestinationShape)
+      return std::unexpected(DestinationShape.error());
+    auto SourceShape = copyShape(Source, Function, Target);
+    if (!SourceShape)
+      return std::unexpected(SourceShape.error());
+    if (DestinationShape->Bank == SourceShape->Bank) {
+      if (DestinationShape->Width && SourceShape->Width &&
+          DestinationShape->Width != SourceShape->Width)
+        return makeUnexpected(ErrorCode::Unsupported,
+                              "RISC-V same-bank COPY has incompatible register widths");
+      return {};
+    }
+
+    const RegisterBankID GPR =
+        RegisterBankID::fromValue(static_cast<std::uint32_t>(RegisterBank::GPR));
+    const RegisterBankID FPR =
+        RegisterBankID::fromValue(static_cast<std::uint32_t>(RegisterBank::FPR));
+    const bool IsCrossBankMove = (DestinationShape->Bank == GPR && SourceShape->Bank == FPR) ||
+                                 (DestinationShape->Bank == FPR && SourceShape->Bank == GPR);
+    if (!IsCrossBankMove)
+      return makeUnexpected(ErrorCode::Unsupported,
+                            "RISC-V COPY crosses unsupported register banks");
+    const auto SupportedWidth = [](std::optional<std::uint32_t> Width) {
+      return !Width || *Width == 32 || *Width == 64;
+    };
+    if (!SupportedWidth(DestinationShape->Width) || !SupportedWidth(SourceShape->Width))
+      return makeUnexpected(ErrorCode::Unsupported,
+                            "RISC-V GPR/FPR COPY requires 32-bit or 64-bit values");
+    return {};
+  }
+
   [[nodiscard]] Expected<std::uint32_t>
   instructionSize(const MachineInstr &Instruction, const MachineFunction &,
                   const TargetDescription &Target) const override {
@@ -726,12 +795,48 @@ public:
       return relaxJAL(Instruction, Offset, Function, Target);
     return false;
   }
+
+private:
+  struct CopyShape final {
+    RegisterBankID Bank;
+    std::optional<std::uint32_t> Width;
+  };
+
+  [[nodiscard]] static Expected<CopyShape> copyShape(Register Reg, const MachineFunction &Function,
+                                                     const TargetDescription &Target) {
+    if (Reg.isVirtual()) {
+      auto Info = Function.registerInfo().virtualRegisterInfo(Reg);
+      if (!Info)
+        return std::unexpected(Info.error());
+      const std::optional<RegisterBankID> &Bank = Info->get().Bank;
+      const std::optional<RegisterClassID> &RegClass = Info->get().RegClass;
+      if (!Bank || !RegClass)
+        return makeUnexpected(ErrorCode::VerificationError,
+                              "RISC-V COPY virtual register is not fully constrained");
+      const RegisterClassDesc *Class = Target.registers().registerClass(*RegClass);
+      if (Class == nullptr)
+        return makeUnexpected(ErrorCode::VerificationError,
+                              "RISC-V COPY references an unknown register class");
+      return CopyShape{*Bank, Class->SizeInBits};
+    }
+
+    const std::optional<PhysicalRegister> Physical = Reg.physicalRegister();
+    if (!Physical || !Target.registers().isKnownPhysicalRegister(*Physical))
+      return makeUnexpected(ErrorCode::VerificationError,
+                            "RISC-V COPY references an unknown physical register");
+    for (const RegisterBankDesc &Bank : Target.registers().registerBanks()) {
+      if (Target.registers().bankContainsRegister(Bank.ID, *Physical))
+        return CopyShape{Bank.ID, std::nullopt};
+    }
+    return makeUnexpected(ErrorCode::VerificationError,
+                          "RISC-V physical register is not assigned to a register bank");
+  }
 };
 
 } // namespace
 
-const TargetInstrInfo &branchInfo() noexcept {
-  static const RISCVBranchInfo Value;
+const TargetInstrInfo &instrInfo() noexcept {
+  static const RISCVInstrInfo Value;
   return Value;
 }
 
diff --git a/backend/lib/Target/RISCV/RISCVInstrInfo.h b/backend/lib/Target/RISCV/RISCVInstrInfo.h
new file mode 100644
index 0000000..62c7723
--- /dev/null
+++ b/backend/lib/Target/RISCV/RISCVInstrInfo.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#ifndef RCC_LIB_TARGET_RISCV_RISCVINSTRINFO_H
+#define RCC_LIB_TARGET_RISCV_RISCVINSTRINFO_H
+
+#include "rcc/CodeGen/TargetInstrInfo.h"
+
+namespace rcc::riscv {
+
+[[nodiscard]] const TargetInstrInfo &instrInfo() noexcept;
+
+} // namespace rcc::riscv
+
+#endif // RCC_LIB_TARGET_RISCV_RISCVINSTRINFO_H
diff --git a/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp b/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp
index 2f8c5d1..9301757 100644
--- a/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp
+++ b/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp
@@ -1,18 +1,18 @@
 // SPDX-License-Identifier: GPL-3.0-or-later
 
+#include "RISCVInstrInfo.h"
 #include "rcc/Target/RISCV/RISCVCodeGen.h"
 
 namespace rcc::riscv {
 
 MachineOptimizationPipelineTargetInfo optimizationPipelineInfo() noexcept {
   return {
-      .SSA = ssaInfo(),
+      .InstrInfo = instrInfo(),
       .Combiner = machineCombinerInfo(),
       .MemoryFolding = memoryFoldingInfo(),
       .FrameLowering = frameLowering(),
       .PseudoExpansion = pseudoExpansionInfo(),
       .SchedulingModel = schedulingModel(),
-      .BranchInfo = branchInfo(),
   };
 }
 
diff --git a/backend/lib/Target/RISCV/RISCVPipeline.cpp b/backend/lib/Target/RISCV/RISCVPipeline.cpp
index 3665db5..08a4653 100644
--- a/backend/lib/Target/RISCV/RISCVPipeline.cpp
+++ b/backend/lib/Target/RISCV/RISCVPipeline.cpp
@@ -2,6 +2,7 @@
 
 #include "rcc/Target/RISCV/RISCVPipeline.h"
 
+#include "RISCVInstrInfo.h"
 #include "rcc/CodeGen/MachineCombiner.h"
 #include "rcc/CodeGen/MachineFunction.h"
 #include "rcc/CodeGen/MachineOptimizationPipeline.h"
@@ -45,10 +46,10 @@ template <typename PassT, typename... ArgumentT>
   auto Added = addSelectedSSAOptimizationPipeline(Pipeline, optimizationPipelineInfo());
   if (!Added)
     return std::unexpected(Added.error());
-  Added = addPass<PHIEliminationPass>(Pipeline, ssaInfo());
+  Added = addPass<PHIEliminationPass>(Pipeline, instrInfo());
   if (!Added)
     return std::unexpected(Added.error());
-  return addPass<TwoAddressRewritePass>(Pipeline, ssaInfo());
+  return addPass<TwoAddressRewritePass>(Pipeline, instrInfo());
 }
 
 [[nodiscard]] Expected<void> addRegisterAllocationPipeline(MachinePassManager &Pipeline) {
@@ -104,13 +105,13 @@ Expected<void> addCanonicalPipeline(MachinePassManager &Pipeline, const MachineF
     if (!Added)
       return std::unexpected(Added.error());
     if (!Function.properties().has(MachineFunctionProperty::NoPHIs)) {
-      Added = addPass<PHIEliminationPass>(Pipeline, ssaInfo());
+      Added = addPass<PHIEliminationPass>(Pipeline, instrInfo());
       if (!Added)
         return std::unexpected(Added.error());
     }
   }
   if (!Function.properties().has(MachineFunctionProperty::TiedOpsRewritten)) {
-    auto Added = addPass<TwoAddressRewritePass>(Pipeline, ssaInfo());
+    auto Added = addPass<TwoAddressRewritePass>(Pipeline, instrInfo());
     if (!Added)
       return std::unexpected(Added.error());
   }