[RISCV] Model typed floating-point register views

7 files changed, 183 insertions, 77 deletions

diff --git a/backend/lib/Target/Description/TargetDescriptionGenerator.cpp b/backend/lib/Target/Description/TargetDescriptionGenerator.cpp
index dd3545b..bd0e794 100644
--- a/backend/lib/Target/Description/TargetDescriptionGenerator.cpp
+++ b/backend/lib/Target/Description/TargetDescriptionGenerator.cpp
@@ -1840,14 +1840,12 @@ private:
     std::unordered_set<std::uint32_t> IDs;
     std::unordered_set<std::string> Symbols;
     std::unordered_set<std::string> Names;
-    std::unordered_set<std::uint32_t> DwarfRegisters;
     for (const SourceRegister &Register : Input.Registers) {
       if (Register.ID == 0 || !isIdentifier(Register.Symbol) || Register.Name.empty() ||
           !IDs.insert(Register.ID).second || !Symbols.insert(Register.Symbol).second ||
-          !Names.insert(lowerASCII(Register.Name)).second ||
-          !DwarfRegisters.insert(Register.DwarfRegister).second || Register.Units.empty()) {
-        fail(Register.Range, "registers require nonzero unique IDs, symbols, canonical names, "
-                             "DWARF numbers, and units");
+          !Names.insert(lowerASCII(Register.Name)).second || Register.Units.empty()) {
+        fail(Register.Range,
+             "registers require nonzero unique IDs, symbols, canonical names, and units");
         return false;
       }
       RegisterBySymbol.emplace(Register.Symbol, Register.ID);
@@ -2900,9 +2898,11 @@ void emitImmediatePredicate(std::ostream &Output, const NormalizedImmediatePredi
     Output << "})},\n";
   }
   Output << "  };\n  Description.CFIRegisters = {\n";
+  std::unordered_set<std::uint32_t> CanonicalDwarfRegisters;
   for (const NormalizedRegister &Register : Model.Registers) {
+    const bool IsCanonical = CanonicalDwarfRegisters.insert(Register.DwarfRegister).second;
     Output << "      {physical(PhysicalRegisterID::" << Register.Symbol << "), "
-           << Register.DwarfRegister << ", true},\n";
+           << Register.DwarfRegister << ", " << (IsCanonical ? "true" : "false") << "},\n";
   }
   Output << "  };\n}\n\n";
 
diff --git a/backend/lib/Target/RISCV/RISCV.rccdesc b/backend/lib/Target/RISCV/RISCV.rccdesc
index 93c94b4..5000d8b 100644
--- a/backend/lib/Target/RISCV/RISCV.rccdesc
+++ b/backend/lib/Target/RISCV/RISCV.rccdesc
@@ -109,38 +109,70 @@ registers:
   - { id: 30, symbol: X29, name: x29, encoding: 29, dwarf_register: 29, units: [{ unit: U_X29, lanes: 1 }], aliases: [t4] }
   - { id: 31, symbol: X30, name: x30, encoding: 30, dwarf_register: 30, units: [{ unit: U_X30, lanes: 1 }], aliases: [t5] }
   - { id: 32, symbol: X31, name: x31, encoding: 31, dwarf_register: 31, units: [{ unit: U_X31, lanes: 1 }], aliases: [t6] }
-  - { id: 33, symbol: F0, name: f0, encoding: 0, dwarf_register: 32, units: [{ unit: U_F0, lanes: 1 }], aliases: [ft0] }
-  - { id: 34, symbol: F1, name: f1, encoding: 1, dwarf_register: 33, units: [{ unit: U_F1, lanes: 1 }], aliases: [ft1] }
-  - { id: 35, symbol: F2, name: f2, encoding: 2, dwarf_register: 34, units: [{ unit: U_F2, lanes: 1 }], aliases: [ft2] }
-  - { id: 36, symbol: F3, name: f3, encoding: 3, dwarf_register: 35, units: [{ unit: U_F3, lanes: 1 }], aliases: [ft3] }
-  - { id: 37, symbol: F4, name: f4, encoding: 4, dwarf_register: 36, units: [{ unit: U_F4, lanes: 1 }], aliases: [ft4] }
-  - { id: 38, symbol: F5, name: f5, encoding: 5, dwarf_register: 37, units: [{ unit: U_F5, lanes: 1 }], aliases: [ft5] }
-  - { id: 39, symbol: F6, name: f6, encoding: 6, dwarf_register: 38, units: [{ unit: U_F6, lanes: 1 }], aliases: [ft6] }
-  - { id: 40, symbol: F7, name: f7, encoding: 7, dwarf_register: 39, units: [{ unit: U_F7, lanes: 1 }], aliases: [ft7] }
-  - { id: 41, symbol: F8, name: f8, encoding: 8, dwarf_register: 40, units: [{ unit: U_F8, lanes: 1 }], aliases: [fs0] }
-  - { id: 42, symbol: F9, name: f9, encoding: 9, dwarf_register: 41, units: [{ unit: U_F9, lanes: 1 }], aliases: [fs1] }
-  - { id: 43, symbol: F10, name: f10, encoding: 10, dwarf_register: 42, units: [{ unit: U_F10, lanes: 1 }], aliases: [fa0] }
-  - { id: 44, symbol: F11, name: f11, encoding: 11, dwarf_register: 43, units: [{ unit: U_F11, lanes: 1 }], aliases: [fa1] }
-  - { id: 45, symbol: F12, name: f12, encoding: 12, dwarf_register: 44, units: [{ unit: U_F12, lanes: 1 }], aliases: [fa2] }
-  - { id: 46, symbol: F13, name: f13, encoding: 13, dwarf_register: 45, units: [{ unit: U_F13, lanes: 1 }], aliases: [fa3] }
-  - { id: 47, symbol: F14, name: f14, encoding: 14, dwarf_register: 46, units: [{ unit: U_F14, lanes: 1 }], aliases: [fa4] }
-  - { id: 48, symbol: F15, name: f15, encoding: 15, dwarf_register: 47, units: [{ unit: U_F15, lanes: 1 }], aliases: [fa5] }
-  - { id: 49, symbol: F16, name: f16, encoding: 16, dwarf_register: 48, units: [{ unit: U_F16, lanes: 1 }], aliases: [fa6] }
-  - { id: 50, symbol: F17, name: f17, encoding: 17, dwarf_register: 49, units: [{ unit: U_F17, lanes: 1 }], aliases: [fa7] }
-  - { id: 51, symbol: F18, name: f18, encoding: 18, dwarf_register: 50, units: [{ unit: U_F18, lanes: 1 }], aliases: [fs2] }
-  - { id: 52, symbol: F19, name: f19, encoding: 19, dwarf_register: 51, units: [{ unit: U_F19, lanes: 1 }], aliases: [fs3] }
-  - { id: 53, symbol: F20, name: f20, encoding: 20, dwarf_register: 52, units: [{ unit: U_F20, lanes: 1 }], aliases: [fs4] }
-  - { id: 54, symbol: F21, name: f21, encoding: 21, dwarf_register: 53, units: [{ unit: U_F21, lanes: 1 }], aliases: [fs5] }
-  - { id: 55, symbol: F22, name: f22, encoding: 22, dwarf_register: 54, units: [{ unit: U_F22, lanes: 1 }], aliases: [fs6] }
-  - { id: 56, symbol: F23, name: f23, encoding: 23, dwarf_register: 55, units: [{ unit: U_F23, lanes: 1 }], aliases: [fs7] }
-  - { id: 57, symbol: F24, name: f24, encoding: 24, dwarf_register: 56, units: [{ unit: U_F24, lanes: 1 }], aliases: [fs8] }
-  - { id: 58, symbol: F25, name: f25, encoding: 25, dwarf_register: 57, units: [{ unit: U_F25, lanes: 1 }], aliases: [fs9] }
-  - { id: 59, symbol: F26, name: f26, encoding: 26, dwarf_register: 58, units: [{ unit: U_F26, lanes: 1 }], aliases: [fs10] }
-  - { id: 60, symbol: F27, name: f27, encoding: 27, dwarf_register: 59, units: [{ unit: U_F27, lanes: 1 }], aliases: [fs11] }
-  - { id: 61, symbol: F28, name: f28, encoding: 28, dwarf_register: 60, units: [{ unit: U_F28, lanes: 1 }], aliases: [ft8] }
-  - { id: 62, symbol: F29, name: f29, encoding: 29, dwarf_register: 61, units: [{ unit: U_F29, lanes: 1 }], aliases: [ft9] }
-  - { id: 63, symbol: F30, name: f30, encoding: 30, dwarf_register: 62, units: [{ unit: U_F30, lanes: 1 }], aliases: [ft10] }
-  - { id: 64, symbol: F31, name: f31, encoding: 31, dwarf_register: 63, units: [{ unit: U_F31, lanes: 1 }], aliases: [ft11] }
+  - { id: 33, symbol: F0_D, name: f0_d, encoding: 0, dwarf_register: 32, units: [{ unit: U_F0, lanes: 1 }], aliases: [ft0] }
+  - { id: 34, symbol: F1_D, name: f1_d, encoding: 1, dwarf_register: 33, units: [{ unit: U_F1, lanes: 1 }], aliases: [ft1] }
+  - { id: 35, symbol: F2_D, name: f2_d, encoding: 2, dwarf_register: 34, units: [{ unit: U_F2, lanes: 1 }], aliases: [ft2] }
+  - { id: 36, symbol: F3_D, name: f3_d, encoding: 3, dwarf_register: 35, units: [{ unit: U_F3, lanes: 1 }], aliases: [ft3] }
+  - { id: 37, symbol: F4_D, name: f4_d, encoding: 4, dwarf_register: 36, units: [{ unit: U_F4, lanes: 1 }], aliases: [ft4] }
+  - { id: 38, symbol: F5_D, name: f5_d, encoding: 5, dwarf_register: 37, units: [{ unit: U_F5, lanes: 1 }], aliases: [ft5] }
+  - { id: 39, symbol: F6_D, name: f6_d, encoding: 6, dwarf_register: 38, units: [{ unit: U_F6, lanes: 1 }], aliases: [ft6] }
+  - { id: 40, symbol: F7_D, name: f7_d, encoding: 7, dwarf_register: 39, units: [{ unit: U_F7, lanes: 1 }], aliases: [ft7] }
+  - { id: 41, symbol: F8_D, name: f8_d, encoding: 8, dwarf_register: 40, units: [{ unit: U_F8, lanes: 1 }], aliases: [fs0] }
+  - { id: 42, symbol: F9_D, name: f9_d, encoding: 9, dwarf_register: 41, units: [{ unit: U_F9, lanes: 1 }], aliases: [fs1] }
+  - { id: 43, symbol: F10_D, name: f10_d, encoding: 10, dwarf_register: 42, units: [{ unit: U_F10, lanes: 1 }], aliases: [fa0] }
+  - { id: 44, symbol: F11_D, name: f11_d, encoding: 11, dwarf_register: 43, units: [{ unit: U_F11, lanes: 1 }], aliases: [fa1] }
+  - { id: 45, symbol: F12_D, name: f12_d, encoding: 12, dwarf_register: 44, units: [{ unit: U_F12, lanes: 1 }], aliases: [fa2] }
+  - { id: 46, symbol: F13_D, name: f13_d, encoding: 13, dwarf_register: 45, units: [{ unit: U_F13, lanes: 1 }], aliases: [fa3] }
+  - { id: 47, symbol: F14_D, name: f14_d, encoding: 14, dwarf_register: 46, units: [{ unit: U_F14, lanes: 1 }], aliases: [fa4] }
+  - { id: 48, symbol: F15_D, name: f15_d, encoding: 15, dwarf_register: 47, units: [{ unit: U_F15, lanes: 1 }], aliases: [fa5] }
+  - { id: 49, symbol: F16_D, name: f16_d, encoding: 16, dwarf_register: 48, units: [{ unit: U_F16, lanes: 1 }], aliases: [fa6] }
+  - { id: 50, symbol: F17_D, name: f17_d, encoding: 17, dwarf_register: 49, units: [{ unit: U_F17, lanes: 1 }], aliases: [fa7] }
+  - { id: 51, symbol: F18_D, name: f18_d, encoding: 18, dwarf_register: 50, units: [{ unit: U_F18, lanes: 1 }], aliases: [fs2] }
+  - { id: 52, symbol: F19_D, name: f19_d, encoding: 19, dwarf_register: 51, units: [{ unit: U_F19, lanes: 1 }], aliases: [fs3] }
+  - { id: 53, symbol: F20_D, name: f20_d, encoding: 20, dwarf_register: 52, units: [{ unit: U_F20, lanes: 1 }], aliases: [fs4] }
+  - { id: 54, symbol: F21_D, name: f21_d, encoding: 21, dwarf_register: 53, units: [{ unit: U_F21, lanes: 1 }], aliases: [fs5] }
+  - { id: 55, symbol: F22_D, name: f22_d, encoding: 22, dwarf_register: 54, units: [{ unit: U_F22, lanes: 1 }], aliases: [fs6] }
+  - { id: 56, symbol: F23_D, name: f23_d, encoding: 23, dwarf_register: 55, units: [{ unit: U_F23, lanes: 1 }], aliases: [fs7] }
+  - { id: 57, symbol: F24_D, name: f24_d, encoding: 24, dwarf_register: 56, units: [{ unit: U_F24, lanes: 1 }], aliases: [fs8] }
+  - { id: 58, symbol: F25_D, name: f25_d, encoding: 25, dwarf_register: 57, units: [{ unit: U_F25, lanes: 1 }], aliases: [fs9] }
+  - { id: 59, symbol: F26_D, name: f26_d, encoding: 26, dwarf_register: 58, units: [{ unit: U_F26, lanes: 1 }], aliases: [fs10] }
+  - { id: 60, symbol: F27_D, name: f27_d, encoding: 27, dwarf_register: 59, units: [{ unit: U_F27, lanes: 1 }], aliases: [fs11] }
+  - { id: 61, symbol: F28_D, name: f28_d, encoding: 28, dwarf_register: 60, units: [{ unit: U_F28, lanes: 1 }], aliases: [ft8] }
+  - { id: 62, symbol: F29_D, name: f29_d, encoding: 29, dwarf_register: 61, units: [{ unit: U_F29, lanes: 1 }], aliases: [ft9] }
+  - { id: 63, symbol: F30_D, name: f30_d, encoding: 30, dwarf_register: 62, units: [{ unit: U_F30, lanes: 1 }], aliases: [ft10] }
+  - { id: 64, symbol: F31_D, name: f31_d, encoding: 31, dwarf_register: 63, units: [{ unit: U_F31, lanes: 1 }], aliases: [ft11] }
+  - { id: 65, symbol: F0_F, name: f0_f, encoding: 0, dwarf_register: 32, units: [{ unit: U_F0, lanes: 1 }] }
+  - { id: 66, symbol: F1_F, name: f1_f, encoding: 1, dwarf_register: 33, units: [{ unit: U_F1, lanes: 1 }] }
+  - { id: 67, symbol: F2_F, name: f2_f, encoding: 2, dwarf_register: 34, units: [{ unit: U_F2, lanes: 1 }] }
+  - { id: 68, symbol: F3_F, name: f3_f, encoding: 3, dwarf_register: 35, units: [{ unit: U_F3, lanes: 1 }] }
+  - { id: 69, symbol: F4_F, name: f4_f, encoding: 4, dwarf_register: 36, units: [{ unit: U_F4, lanes: 1 }] }
+  - { id: 70, symbol: F5_F, name: f5_f, encoding: 5, dwarf_register: 37, units: [{ unit: U_F5, lanes: 1 }] }
+  - { id: 71, symbol: F6_F, name: f6_f, encoding: 6, dwarf_register: 38, units: [{ unit: U_F6, lanes: 1 }] }
+  - { id: 72, symbol: F7_F, name: f7_f, encoding: 7, dwarf_register: 39, units: [{ unit: U_F7, lanes: 1 }] }
+  - { id: 73, symbol: F8_F, name: f8_f, encoding: 8, dwarf_register: 40, units: [{ unit: U_F8, lanes: 1 }] }
+  - { id: 74, symbol: F9_F, name: f9_f, encoding: 9, dwarf_register: 41, units: [{ unit: U_F9, lanes: 1 }] }
+  - { id: 75, symbol: F10_F, name: f10_f, encoding: 10, dwarf_register: 42, units: [{ unit: U_F10, lanes: 1 }] }
+  - { id: 76, symbol: F11_F, name: f11_f, encoding: 11, dwarf_register: 43, units: [{ unit: U_F11, lanes: 1 }] }
+  - { id: 77, symbol: F12_F, name: f12_f, encoding: 12, dwarf_register: 44, units: [{ unit: U_F12, lanes: 1 }] }
+  - { id: 78, symbol: F13_F, name: f13_f, encoding: 13, dwarf_register: 45, units: [{ unit: U_F13, lanes: 1 }] }
+  - { id: 79, symbol: F14_F, name: f14_f, encoding: 14, dwarf_register: 46, units: [{ unit: U_F14, lanes: 1 }] }
+  - { id: 80, symbol: F15_F, name: f15_f, encoding: 15, dwarf_register: 47, units: [{ unit: U_F15, lanes: 1 }] }
+  - { id: 81, symbol: F16_F, name: f16_f, encoding: 16, dwarf_register: 48, units: [{ unit: U_F16, lanes: 1 }] }
+  - { id: 82, symbol: F17_F, name: f17_f, encoding: 17, dwarf_register: 49, units: [{ unit: U_F17, lanes: 1 }] }
+  - { id: 83, symbol: F18_F, name: f18_f, encoding: 18, dwarf_register: 50, units: [{ unit: U_F18, lanes: 1 }] }
+  - { id: 84, symbol: F19_F, name: f19_f, encoding: 19, dwarf_register: 51, units: [{ unit: U_F19, lanes: 1 }] }
+  - { id: 85, symbol: F20_F, name: f20_f, encoding: 20, dwarf_register: 52, units: [{ unit: U_F20, lanes: 1 }] }
+  - { id: 86, symbol: F21_F, name: f21_f, encoding: 21, dwarf_register: 53, units: [{ unit: U_F21, lanes: 1 }] }
+  - { id: 87, symbol: F22_F, name: f22_f, encoding: 22, dwarf_register: 54, units: [{ unit: U_F22, lanes: 1 }] }
+  - { id: 88, symbol: F23_F, name: f23_f, encoding: 23, dwarf_register: 55, units: [{ unit: U_F23, lanes: 1 }] }
+  - { id: 89, symbol: F24_F, name: f24_f, encoding: 24, dwarf_register: 56, units: [{ unit: U_F24, lanes: 1 }] }
+  - { id: 90, symbol: F25_F, name: f25_f, encoding: 25, dwarf_register: 57, units: [{ unit: U_F25, lanes: 1 }] }
+  - { id: 91, symbol: F26_F, name: f26_f, encoding: 26, dwarf_register: 58, units: [{ unit: U_F26, lanes: 1 }] }
+  - { id: 92, symbol: F27_F, name: f27_f, encoding: 27, dwarf_register: 59, units: [{ unit: U_F27, lanes: 1 }] }
+  - { id: 93, symbol: F28_F, name: f28_f, encoding: 28, dwarf_register: 60, units: [{ unit: U_F28, lanes: 1 }] }
+  - { id: 94, symbol: F29_F, name: f29_f, encoding: 29, dwarf_register: 61, units: [{ unit: U_F29, lanes: 1 }] }
+  - { id: 95, symbol: F30_F, name: f30_f, encoding: 30, dwarf_register: 62, units: [{ unit: U_F30, lanes: 1 }] }
+  - { id: 96, symbol: F31_F, name: f31_f, encoding: 31, dwarf_register: 63, units: [{ unit: U_F31, lanes: 1 }] }
 
 register_banks:
   - { id: 1, symbol: GPR, name: GPRB, maximum_size_bits: 64 }
@@ -178,8 +210,8 @@ register_classes:
     spill_size_bits: 64
     spill_alignment_bits: 64
     lanes: 1
-    registers: [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]
-    allocation_order: [F10, F11, F12, F13, F14, F15, F16, F17, F0, F1, F2, F3, F4, F5, F6, F7, F28, F29, F30, F31, F8, F9, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27]
+    registers: [F0_D, F1_D, F2_D, F3_D, F4_D, F5_D, F6_D, F7_D, F8_D, F9_D, F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D, F28_D, F29_D, F30_D, F31_D]
+    allocation_order: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D, F0_D, F1_D, F2_D, F3_D, F4_D, F5_D, F6_D, F7_D, F28_D, F29_D, F30_D, F31_D, F8_D, F9_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D]
   -
     id: 4
     symbol: FPR64C
@@ -189,8 +221,8 @@ register_classes:
     spill_size_bits: 64
     spill_alignment_bits: 64
     lanes: 1
-    registers: [F8, F9, F10, F11, F12, F13, F14, F15]
-    allocation_order: [F10, F11, F12, F13, F14, F15, F8, F9]
+    registers: [F8_D, F9_D, F10_D, F11_D, F12_D, F13_D, F14_D, F15_D]
+    allocation_order: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F8_D, F9_D]
   -
     id: 5
     symbol: FPR32
@@ -200,8 +232,8 @@ register_classes:
     spill_size_bits: 32
     spill_alignment_bits: 32
     lanes: 1
-    registers: [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]
-    allocation_order: [F10, F11, F12, F13, F14, F15, F16, F17, F0, F1, F2, F3, F4, F5, F6, F7, F28, F29, F30, F31, F8, F9, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27]
+    registers: [F0_F, F1_F, F2_F, F3_F, F4_F, F5_F, F6_F, F7_F, F8_F, F9_F, F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F16_F, F17_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F, F28_F, F29_F, F30_F, F31_F]
+    allocation_order: [F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F16_F, F17_F, F0_F, F1_F, F2_F, F3_F, F4_F, F5_F, F6_F, F7_F, F28_F, F29_F, F30_F, F31_F, F8_F, F9_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F]
   -
     id: 6
     symbol: FPR32C
@@ -211,8 +243,8 @@ register_classes:
     spill_size_bits: 32
     spill_alignment_bits: 32
     lanes: 1
-    registers: [F8, F9, F10, F11, F12, F13, F14, F15]
-    allocation_order: [F10, F11, F12, F13, F14, F15, F8, F9]
+    registers: [F8_F, F9_F, F10_F, F11_F, F12_F, F13_F, F14_F, F15_F]
+    allocation_order: [F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F8_F, F9_F]
   -
     id: 7
     symbol: GPR_NX0
@@ -242,7 +274,7 @@ register_masks:
     preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27]
   -
     name: CSR_ILP32D_LP64D
-    preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, F8, F9, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27]
+    preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, F8_D, F9_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D, F8_F, F9_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F]
 
 mir_operand_flags:
   direct_mask: 31
@@ -278,9 +310,9 @@ calling_conventions:
     integer_register_class: GPR
     floating_register_class: FPR64
     integer_argument_registers: [X10, X11, X12, X13, X14, X15, X16, X17]
-    floating_argument_registers: [F10, F11, F12, F13, F14, F15, F16, F17]
+    floating_argument_registers: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D]
     integer_return_registers: [X10, X11]
-    floating_return_registers: [F10, F11]
+    floating_return_registers: [F10_D, F11_D]
     preserved_mask: CSR_ILP32D_LP64D
     stack_alignment_bytes: 16
     stack_argument_alignment_bytes: 16
diff --git a/backend/lib/Target/RISCV/RISCVCallLowering.cpp b/backend/lib/Target/RISCV/RISCVCallLowering.cpp
index 60bf6f2..5da3fc8 100644
--- a/backend/lib/Target/RISCV/RISCVCallLowering.cpp
+++ b/backend/lib/Target/RISCV/RISCVCallLowering.cpp
@@ -70,6 +70,26 @@ constexpr std::uint32_t AllowedDirectCallFlags =
          (*Semantics == FloatSemantics::IEEESingle || *Semantics == FloatSemantics::IEEEDouble);
 }
 
+[[nodiscard]] Expected<PhysicalRegister> floatingRegisterView(PhysicalRegister DoubleView,
+                                                              LLT Type) {
+  if (!isSupportedFloat(Type)) {
+    return makeUnexpected(ErrorCode::InvalidArgument,
+                          "RISC-V floating-register view requires f32 or f64");
+  }
+  if (Type.scalarBitWidth() == 64)
+    return DoubleView;
+
+  constexpr std::uint32_t FirstDouble = static_cast<std::uint32_t>(PhysicalRegisterID::F0_D);
+  constexpr std::uint32_t LastDouble = static_cast<std::uint32_t>(PhysicalRegisterID::F31_D);
+  constexpr std::uint32_t FirstSingle = static_cast<std::uint32_t>(PhysicalRegisterID::F0_F);
+  const std::uint32_t Number = DoubleView.number();
+  if (Number < FirstDouble || Number > LastDouble) {
+    return makeUnexpected(ErrorCode::InternalError,
+                          "RISC-V ABI floating register is not an FPR64 view");
+  }
+  return PhysicalRegister::create(FirstSingle + Number - FirstDouble);
+}
+
 [[nodiscard]] bool requiresIntegerTransport(const ABIValue &Value) noexcept {
   return !isSupportedFloat(Value.Type) || Value.Flags.has(ABIValueFlag::ByVal) ||
          Value.Flags.has(ABIValueFlag::StructReturn) || Value.Flags.has(ABIValueFlag::Indirect);
@@ -301,14 +321,19 @@ assignArguments(std::span<const ABIValue> Values, std::size_t FixedArgumentCount
     if (CanUsePreferredAggregate) {
       for (std::size_t Fragment = 0; Fragment < GroupSize; ++Fragment) {
         const ABIValue &Value = Values[Index + Fragment];
-        Expected<CCAssignment> Assignment =
-            requiresIntegerTransport(Value)
-                ? registerAssignment(Value, Index + Fragment,
-                                     Convention.IntegerArgumentRegisters[State.GPR++], *I64, false,
-                                     false)
-                : registerAssignment(Value, Index + Fragment,
-                                     Convention.FloatingArgumentRegisters[State.FPR++], Value.Type,
-                                     false, false);
+        Expected<CCAssignment> Assignment = makeUnexpected(
+            ErrorCode::InternalError, "RISC-V ABI argument assignment was not initialized");
+        if (requiresIntegerTransport(Value)) {
+          Assignment = registerAssignment(Value, Index + Fragment,
+                                          Convention.IntegerArgumentRegisters[State.GPR++], *I64,
+                                          false, false);
+        } else {
+          auto View =
+              floatingRegisterView(Convention.FloatingArgumentRegisters[State.FPR++], Value.Type);
+          if (!View)
+            return std::unexpected(View.error());
+          Assignment = registerAssignment(Value, Index + Fragment, *View, Value.Type, false, false);
+        }
         if (!Assignment)
           return std::unexpected(Assignment.error());
         Result.Assignments.push_back(*Assignment);
@@ -413,8 +438,10 @@ assignReturns(std::span<const ABIValue> Values, bool RequireRegisters,
     Expected<CCAssignment> Assignment = makeUnexpected(
         ErrorCode::Unsupported, "RISC-V calling convention has no return register available");
     if (UseFloatingRegister) {
-      Assignment = registerAssignment(Value, Index, Convention.FloatingReturnRegisters[FPR++],
-                                      Value.Type, false, false);
+      auto View = floatingRegisterView(Convention.FloatingReturnRegisters[FPR++], Value.Type);
+      if (!View)
+        return std::unexpected(View.error());
+      Assignment = registerAssignment(Value, Index, *View, Value.Type, false, false);
     } else if (GPR < Convention.IntegerReturnRegisters.size()) {
       Assignment = registerAssignment(Value, Index, Convention.IntegerReturnRegisters[GPR++], *I64,
                                       false, isSupportedFloat(Value.Type));
diff --git a/backend/lib/Target/RISCV/RISCVFrameLowering.cpp b/backend/lib/Target/RISCV/RISCVFrameLowering.cpp
index 4ba5540..513788f 100644
--- a/backend/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/backend/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -320,15 +320,15 @@ struct CallFrameRequirement final {
 
 [[nodiscard]] std::array<PhysicalRegisterID, 25> saveOrder() noexcept {
   return {
-      PhysicalRegisterID::X1,  PhysicalRegisterID::X8,  PhysicalRegisterID::X9,
-      PhysicalRegisterID::X18, PhysicalRegisterID::X19, PhysicalRegisterID::X20,
-      PhysicalRegisterID::X21, PhysicalRegisterID::X22, PhysicalRegisterID::X23,
-      PhysicalRegisterID::X24, PhysicalRegisterID::X25, PhysicalRegisterID::X26,
-      PhysicalRegisterID::X27, PhysicalRegisterID::F8,  PhysicalRegisterID::F9,
-      PhysicalRegisterID::F18, PhysicalRegisterID::F19, PhysicalRegisterID::F20,
-      PhysicalRegisterID::F21, PhysicalRegisterID::F22, PhysicalRegisterID::F23,
-      PhysicalRegisterID::F24, PhysicalRegisterID::F25, PhysicalRegisterID::F26,
-      PhysicalRegisterID::F27,
+      PhysicalRegisterID::X1,    PhysicalRegisterID::X8,    PhysicalRegisterID::X9,
+      PhysicalRegisterID::X18,   PhysicalRegisterID::X19,   PhysicalRegisterID::X20,
+      PhysicalRegisterID::X21,   PhysicalRegisterID::X22,   PhysicalRegisterID::X23,
+      PhysicalRegisterID::X24,   PhysicalRegisterID::X25,   PhysicalRegisterID::X26,
+      PhysicalRegisterID::X27,   PhysicalRegisterID::F8_D,  PhysicalRegisterID::F9_D,
+      PhysicalRegisterID::F18_D, PhysicalRegisterID::F19_D, PhysicalRegisterID::F20_D,
+      PhysicalRegisterID::F21_D, PhysicalRegisterID::F22_D, PhysicalRegisterID::F23_D,
+      PhysicalRegisterID::F24_D, PhysicalRegisterID::F25_D, PhysicalRegisterID::F26_D,
+      PhysicalRegisterID::F27_D,
   };
 }
 
@@ -993,7 +993,7 @@ emitSavedRegisterCFI(MachineIRBuilder &Builder, const TargetDescription &Target,
 
 [[nodiscard]] Expected<MachineInstr *>
 emitCalleeSave(MachineIRBuilder &Builder, PhysicalRegister Reg, FrameIndex Index, bool Restore) {
-  const bool IsFPR = Reg.number() >= static_cast<std::uint32_t>(PhysicalRegisterID::F0);
+  const bool IsFPR = Reg.number() >= static_cast<std::uint32_t>(PhysicalRegisterID::F0_D);
   const InstructionOpcode OpcodeValue =
       Restore ? (IsFPR ? InstructionOpcode::FLD : InstructionOpcode::LD)
               : (IsFPR ? InstructionOpcode::FSD : InstructionOpcode::SD);
diff --git a/backend/lib/Target/RISCV/RISCVInstPrinter.cpp b/backend/lib/Target/RISCV/RISCVInstPrinter.cpp
index ba3e509..4699835 100644
--- a/backend/lib/Target/RISCV/RISCVInstPrinter.cpp
+++ b/backend/lib/Target/RISCV/RISCVInstPrinter.cpp
@@ -90,7 +90,10 @@ constexpr std::array LinearFormats{
       return makeUnexpected(ErrorCode::AssemblyLoweringFailed,
                             "RISC-V MC instruction references an unknown register");
     }
-    return std::string(*Name);
+    std::string AssemblyName(*Name);
+    if (AssemblyName.ends_with("_f") || AssemblyName.ends_with("_d"))
+      AssemblyName.resize(AssemblyName.size() - 2);
+    return AssemblyName;
   }
   if (const std::int64_t *Immediate = Operand.immediateValue(); Immediate != nullptr)
     return std::to_string(*Immediate);
diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
index aee09a9..055b67b 100644
--- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
+++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
@@ -81,10 +81,14 @@ createStackMemoryOperand(MachineIRBuilder &Builder, FrameIndex StackSlot, Memory
       PhysicalRegisterID::X25, PhysicalRegisterID::X26, PhysicalRegisterID::X27,
   };
   const std::array FPRs{
-      PhysicalRegisterID::F8,  PhysicalRegisterID::F9,  PhysicalRegisterID::F18,
-      PhysicalRegisterID::F19, PhysicalRegisterID::F20, PhysicalRegisterID::F21,
-      PhysicalRegisterID::F22, PhysicalRegisterID::F23, PhysicalRegisterID::F24,
-      PhysicalRegisterID::F25, PhysicalRegisterID::F26, PhysicalRegisterID::F27,
+      PhysicalRegisterID::F8_D,  PhysicalRegisterID::F9_D,  PhysicalRegisterID::F18_D,
+      PhysicalRegisterID::F19_D, PhysicalRegisterID::F20_D, PhysicalRegisterID::F21_D,
+      PhysicalRegisterID::F22_D, PhysicalRegisterID::F23_D, PhysicalRegisterID::F24_D,
+      PhysicalRegisterID::F25_D, PhysicalRegisterID::F26_D, PhysicalRegisterID::F27_D,
+      PhysicalRegisterID::F8_F,  PhysicalRegisterID::F9_F,  PhysicalRegisterID::F18_F,
+      PhysicalRegisterID::F19_F, PhysicalRegisterID::F20_F, PhysicalRegisterID::F21_F,
+      PhysicalRegisterID::F22_F, PhysicalRegisterID::F23_F, PhysicalRegisterID::F24_F,
+      PhysicalRegisterID::F25_F, PhysicalRegisterID::F26_F, PhysicalRegisterID::F27_F,
   };
   const auto Matches = [Number](PhysicalRegisterID ID) {
     return Number == static_cast<std::uint32_t>(ID);
@@ -96,9 +100,12 @@ createStackMemoryOperand(MachineIRBuilder &Builder, FrameIndex StackSlot, Memory
   const std::uint32_t Number = Reg.number();
   const std::uint32_t X8 = static_cast<std::uint32_t>(PhysicalRegisterID::X8);
   const std::uint32_t X15 = static_cast<std::uint32_t>(PhysicalRegisterID::X15);
-  const std::uint32_t F8 = static_cast<std::uint32_t>(PhysicalRegisterID::F8);
-  const std::uint32_t F15 = static_cast<std::uint32_t>(PhysicalRegisterID::F15);
-  return (Number >= X8 && Number <= X15) || (Number >= F8 && Number <= F15);
+  const std::uint32_t F8D = static_cast<std::uint32_t>(PhysicalRegisterID::F8_D);
+  const std::uint32_t F15D = static_cast<std::uint32_t>(PhysicalRegisterID::F15_D);
+  const std::uint32_t F8F = static_cast<std::uint32_t>(PhysicalRegisterID::F8_F);
+  const std::uint32_t F15F = static_cast<std::uint32_t>(PhysicalRegisterID::F15_F);
+  return (Number >= X8 && Number <= X15) || (Number >= F8D && Number <= F15D) ||
+         (Number >= F8F && Number <= F15F);
 }
 
 class RISCVRegisterAllocationInfo final : public TargetRegisterAllocationInfo {
diff --git a/backend/lib/Target/RISCV/RISCVTarget.cpp b/backend/lib/Target/RISCV/RISCVTarget.cpp
index 299b5ab..090d0bc 100644
--- a/backend/lib/Target/RISCV/RISCVTarget.cpp
+++ b/backend/lib/Target/RISCV/RISCVTarget.cpp
@@ -63,6 +63,41 @@ physicalRegisters(std::initializer_list<PhysicalRegisterID> IDs) {
   };
 }
 
+[[nodiscard]] Expected<void> appendRISCVSubRegisterInfo(TargetRegisterInfoDesc &Description) {
+  constexpr SubRegIndex FPR32SubReg = SubRegIndex::fromValue(1);
+  constexpr std::uint32_t FirstDouble = static_cast<std::uint32_t>(PhysicalRegisterID::F0_D);
+  constexpr std::uint32_t LastDouble = static_cast<std::uint32_t>(PhysicalRegisterID::F31_D);
+  constexpr std::uint32_t FirstSingle = static_cast<std::uint32_t>(PhysicalRegisterID::F0_F);
+  constexpr std::uint32_t LastSingle = static_cast<std::uint32_t>(PhysicalRegisterID::F31_F);
+  static_assert(LastDouble - FirstDouble == 31);
+  static_assert(LastSingle - FirstSingle == 31);
+
+  Description.SubRegIndices.push_back({FPR32SubReg, "sub_32", LaneMask::fromRaw(1), 32, 0});
+  for (std::uint32_t Index = 0; Index != 32; ++Index) {
+    auto Double = PhysicalRegister::create(FirstDouble + Index);
+    auto Single = PhysicalRegister::create(FirstSingle + Index);
+    if (!Double || !Single)
+      return makeUnexpected(ErrorCode::InternalError, "RISC-V FPR view ID is invalid");
+    Description.PhysicalSubRegisters.push_back({*Double, FPR32SubReg, *Single});
+  }
+
+  const auto AddClassMapping = [&](RegisterClass Super, RegisterClass Sub) -> Expected<void> {
+    const RegisterClassID SuperID = RegisterClassID::fromValue(static_cast<std::uint32_t>(Super));
+    const RegisterClassID SubID = RegisterClassID::fromValue(static_cast<std::uint32_t>(Sub));
+    const auto Position =
+        std::ranges::find(Description.RegisterClasses, SuperID, &RegisterClassDesc::ID);
+    if (Position == Description.RegisterClasses.end()) {
+      return makeUnexpected(ErrorCode::InternalError, "RISC-V FPR super-register class is missing");
+    }
+    Position->SupportedSubRegs.push_back(FPR32SubReg);
+    Description.SubRegClassMappings.push_back({SuperID, FPR32SubReg, SubID});
+    return {};
+  };
+  if (auto Result = AddClassMapping(RegisterClass::FPR64, RegisterClass::FPR32); !Result)
+    return Result;
+  return AddClassMapping(RegisterClass::FPR64C, RegisterClass::FPR32C);
+}
+
 [[nodiscard]] std::shared_ptr<const RegisterMask>
 makePreservedMask(std::initializer_list<PhysicalRegisterID> Preserved) {
   std::vector<std::uint64_t> Words;
@@ -87,6 +122,8 @@ Expected<PhysicalRegister> physicalRegister(PhysicalRegisterID ID) {
 Expected<TargetRegisterInfo> createRegisterInfo() {
   TargetRegisterInfoDesc Description;
   appendGeneratedRegisterInfo(Description);
+  if (auto Result = appendRISCVSubRegisterInfo(Description); !Result)
+    return std::unexpected(Result.error());
   return TargetRegisterInfo::create(std::move(Description));
 }