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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 17:37:09 +0000 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 17:37:09 +0000 |
| commit | 693c861fb5fecbfc47f3434c2469eeae65ec6cee (patch) | |
| tree | 5464d8543546be5c432b4b9a08220feee192789c /backend/unittests/CodeGen/MachineMetadataTest.cpp | |
| parent | f29e711b76e7c6bb436111609fa0b14e5c448fb7 (diff) | |
| download | rcc-project-693c861fb5fecbfc47f3434c2469eeae65ec6cee.tar.gz rcc-project-693c861fb5fecbfc47f3434c2469eeae65ec6cee.tar.xz | |
test(core): fix WB stage tests after naming and logic refactor
- Renamed `wb_reg_write_data` to `wb_rd_wdata` in all assertions to match the updated module ports.
- Renamed `wb_reg_write_addr` to `wb_rd_addr` in all assertions.
- Initialized the new `mem_wb_pc_plus_4` input in the testbench setup to correctly test the JAL/JALR datapath.
- Added assertions to explicitly test that `wb_reg_write_en` and `csr_req` are gated when an exception occurs.
Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
Diffstat (limited to 'backend/unittests/CodeGen/MachineMetadataTest.cpp')
0 files changed, 0 insertions, 0 deletions