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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 02:14:52 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 02:14:52 +0800 |
| commit | 16b269164d072f3c0be713decc977c5c5f44f5e8 (patch) | |
| tree | 5c33b79939edd899da6a72c4f22017f99dfd2444 /backend/unittests/CodeGen | |
| parent | ed9afd0d9e2ecb202872b6ea4ebe5690860f9b84 (diff) | |
| download | rcc-project-16b269164d072f3c0be713decc977c5c5f44f5e8.tar.gz rcc-project-16b269164d072f3c0be713decc977c5c5f44f5e8.tar.xz | |
[RISCV] Legalize G_VAARG
Diffstat (limited to 'backend/unittests/CodeGen')
| -rw-r--r-- | backend/unittests/CodeGen/GenericOpcodesTest.cpp | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/backend/unittests/CodeGen/GenericOpcodesTest.cpp b/backend/unittests/CodeGen/GenericOpcodesTest.cpp index c9ed8d5..4527004 100644 --- a/backend/unittests/CodeGen/GenericOpcodesTest.cpp +++ b/backend/unittests/CodeGen/GenericOpcodesTest.cpp @@ -649,21 +649,12 @@ void testInstructionMemorySemantics(TestContext &Context) { VarArgOperands.push_back(rcc::MachineOperand::immediate(8)); rcc::MachineInstr &VarArg = createInstruction(**Function, rcc::GenericOpcode::G_VAARG, std::move(VarArgOperands)); + Context.expect(Set->validateInstruction(VarArg, (*Function)->registerInfo()).has_value(), + "G_VAARG must accept LLVM's canonical form without MMOs"); addMemOperand(**Function, VarArg, memoryDescription({rcc::MemoryAccessFlag::Load}, 8)); addMemOperand(**Function, VarArg, memoryDescription({rcc::MemoryAccessFlag::Store}, 8)); - Context.expect(Set->validateInstruction(VarArg, (*Function)->registerInfo()).has_value(), - "G_VAARG must accept separate value-load and list-update MMOs"); - - std::vector<rcc::MachineOperand> CombinedVarArgOperands; - CombinedVarArgOperands.push_back(registerOperand(Dst64, true)); - CombinedVarArgOperands.push_back(registerOperand(Address0, false)); - CombinedVarArgOperands.push_back(rcc::MachineOperand::immediate(8)); - rcc::MachineInstr &CombinedVarArg = - createInstruction(**Function, rcc::GenericOpcode::G_VAARG, std::move(CombinedVarArgOperands)); - addMemOperand(**Function, CombinedVarArg, - memoryDescription({rcc::MemoryAccessFlag::Load, rcc::MemoryAccessFlag::Store}, 8)); - Context.expect(!Set->validateInstruction(CombinedVarArg, (*Function)->registerInfo()), - "G_VAARG must reject a combined read-write MMO in place of two accesses"); + Context.expect(!Set->validateInstruction(VarArg, (*Function)->registerInfo()), + "G_VAARG must reject MMOs before legalization"); std::vector<rcc::MachineOperand> MemoryTransferOperands; MemoryTransferOperands.push_back(registerOperand(Address0, false)); @@ -706,6 +697,7 @@ void testSemanticFlags(TestContext &Context) { const auto *Load = Find(rcc::GenericOpcode::G_LOAD); const auto *Atomic = Find(rcc::GenericOpcode::G_ATOMIC_CMPXCHG); + const auto *VarArg = Find(rcc::GenericOpcode::G_VAARG); const auto *Branch = Find(rcc::GenericOpcode::G_BRINDIRECT); const auto *Strict = Find(rcc::GenericOpcode::G_STRICT_FMA); const auto *InlineAsm = Find(rcc::GenericOpcode::INLINEASM); @@ -714,6 +706,8 @@ void testSemanticFlags(TestContext &Context) { Load->RequiresMemoryOperands && Atomic != nullptr && Atomic->Flags.has(rcc::InstructionFlag::MayLoad) && Atomic->Flags.has(rcc::InstructionFlag::MayStore) && Atomic->RequiresMemoryOperands && + VarArg != nullptr && VarArg->Flags.has(rcc::InstructionFlag::MayLoad) && + VarArg->Flags.has(rcc::InstructionFlag::MayStore) && !VarArg->RequiresMemoryOperands && Branch != nullptr && Branch->Flags.has(rcc::InstructionFlag::Terminator) && Branch->Flags.has(rcc::InstructionFlag::IndirectBranch) && Branch->Flags.has(rcc::InstructionFlag::Barrier) && Strict != nullptr && |