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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 03:02:45 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 03:02:45 +0800 |
| commit | 888e9b5bb57a79f4eee88a7926cb859e04823361 (patch) | |
| tree | 58cba25d087e43862ba7de139b49e126f6d7445c /backend/unittests/Target/RISCVMCEncodingCoverageTest.cpp | |
| parent | 23dad063b9172982467b69650ae334bbec63e759 (diff) | |
| download | rcc-project-888e9b5bb57a79f4eee88a7926cb859e04823361.tar.gz rcc-project-888e9b5bb57a79f4eee88a7926cb859e04823361.tar.xz | |
[RISCV] Add Zba and Zbb instruction descriptions
Diffstat (limited to 'backend/unittests/Target/RISCVMCEncodingCoverageTest.cpp')
| -rw-r--r-- | backend/unittests/Target/RISCVMCEncodingCoverageTest.cpp | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/backend/unittests/Target/RISCVMCEncodingCoverageTest.cpp b/backend/unittests/Target/RISCVMCEncodingCoverageTest.cpp index d66d19d..1a7157a 100644 --- a/backend/unittests/Target/RISCVMCEncodingCoverageTest.cpp +++ b/backend/unittests/Target/RISCVMCEncodingCoverageTest.cpp @@ -117,6 +117,7 @@ createStandardFixture(const rcc::InstructionDescriptor &Descriptor, addRegister(Result, Descriptor, Source1Encoding); addImmediate(Result, (Encoding >> 12U) & 7U); return Result; + case RD_RS1: case RD_FRS1: addRegister(Result, Descriptor, DestinationEncoding); addRegister(Result, Descriptor, Source1Encoding); @@ -138,12 +139,17 @@ createStandardFixture(const rcc::InstructionDescriptor &Descriptor, addImmediate(Result, (Encoding >> 20U) & 0xfU); return Result; } + if (Format == RD_RS1) { + addRegister(Result, Descriptor, DestinationEncoding); + addRegister(Result, Descriptor, Source1Encoding); + return Result; + } const bool FloatingDestination = Format == FRD_OFFSET_RS1; if (Format != RD_RS1_IMM && Format != RD_OFFSET_RS1 && !FloatingDestination) return fixtureError("unsupported I-type reference fixture format"); addRegister(Result, Descriptor, DestinationEncoding); addRegister(Result, Descriptor, Source1Encoding); - const bool Shift64 = Opcode == SLLI || Opcode == SRLI || Opcode == SRAI; + const bool Shift64 = Opcode == SLLI || Opcode == SLLI_UW || Opcode == SRLI || Opcode == SRAI; const bool Shift32 = Opcode == SLLIW || Opcode == SRLIW || Opcode == SRAIW; if (Shift64) addImmediate(Result, (Encoding >> 20U) & 0x3fU); @@ -387,8 +393,8 @@ int main() { } const std::span<const rcc::riscv::AssemblyInstructionInfo> Instructions = rcc::riscv::assemblyInstructions(); - if (Instructions.size() != 195) { - std::cerr << "RV64GC encoding coverage does not contain all 195 instructions\n"; + if (Instructions.size() != 211) { + std::cerr << "RISC-V encoding coverage does not contain all 211 instructions\n"; return 1; } |