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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-11 23:44:57 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-11 23:44:57 +0800 |
| commit | e6cd1347cc2c76babe56842e1b7bd05d68fe9584 (patch) | |
| tree | d00769b50841cbcea907b76ac006b366147325dc /backend/unittests/Target/RISCVRegisterAllocationTest.cpp | |
| parent | 234d7d3bec020103e46daaff39d207d978479730 (diff) | |
| download | rcc-project-e6cd1347cc2c76babe56842e1b7bd05d68fe9584.tar.gz rcc-project-e6cd1347cc2c76babe56842e1b7bd05d68fe9584.tar.xz | |
[RISCV] Model typed floating-point register views
Diffstat (limited to 'backend/unittests/Target/RISCVRegisterAllocationTest.cpp')
| -rw-r--r-- | backend/unittests/Target/RISCVRegisterAllocationTest.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/backend/unittests/Target/RISCVRegisterAllocationTest.cpp b/backend/unittests/Target/RISCVRegisterAllocationTest.cpp index 72cce51..299308c 100644 --- a/backend/unittests/Target/RISCVRegisterAllocationTest.cpp +++ b/backend/unittests/Target/RISCVRegisterAllocationTest.cpp @@ -264,16 +264,16 @@ void testTargetHooks(TestContext &Context, const rcc::TargetDescription &Target) Info.emitSpill(Builder, physical(rcc::riscv::PhysicalRegisterID::X5), registerClass(rcc::riscv::RegisterClass::GPR), *Slot, rcc::LaneMask::all()); auto F32Reload = - Info.emitReload(Builder, physical(rcc::riscv::PhysicalRegisterID::F10), + Info.emitReload(Builder, physical(rcc::riscv::PhysicalRegisterID::F10_F), registerClass(rcc::riscv::RegisterClass::FPR32), *Slot, rcc::LaneMask::all()); auto F32Spill = - Info.emitSpill(Builder, physical(rcc::riscv::PhysicalRegisterID::F10), + Info.emitSpill(Builder, physical(rcc::riscv::PhysicalRegisterID::F10_F), registerClass(rcc::riscv::RegisterClass::FPR32), *Slot, rcc::LaneMask::all()); auto F64Reload = - Info.emitReload(Builder, physical(rcc::riscv::PhysicalRegisterID::F11), + Info.emitReload(Builder, physical(rcc::riscv::PhysicalRegisterID::F11_D), registerClass(rcc::riscv::RegisterClass::FPR64), *Slot, rcc::LaneMask::all()); auto F64Spill = - Info.emitSpill(Builder, physical(rcc::riscv::PhysicalRegisterID::F11), + Info.emitSpill(Builder, physical(rcc::riscv::PhysicalRegisterID::F11_D), registerClass(rcc::riscv::RegisterClass::FPR64), *Slot, rcc::LaneMask::all()); Context.expect(GPRReload && GPRSpill && F32Reload && F32Spill && F64Reload && F64Spill && (*GPRReload)->opcode() == targetOpcode(rcc::riscv::InstructionOpcode::LD) && |