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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-19 17:25:55 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-19 17:25:55 +0800
commit5c5a71428a93fb225f0057790f41697fe2a0df92 (patch)
tree18d1a5214936c767e079e9be0864e9496db2b4ca /backend/unittests
parent0dc24902b4d01b939160946098a8a3bb404b9d73 (diff)
downloadrcc-project-5c5a71428a93fb225f0057790f41697fe2a0df92.tar.gz
rcc-project-5c5a71428a93fb225f0057790f41697fe2a0df92.tar.xz
[CodeGen] Remove non-LLVM machine DCE placements
Diffstat (limited to 'backend/unittests')
-rw-r--r--backend/unittests/Target/RISCVLateCodeGenTest.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/backend/unittests/Target/RISCVLateCodeGenTest.cpp b/backend/unittests/Target/RISCVLateCodeGenTest.cpp
index 0deebc6..2b165c4 100644
--- a/backend/unittests/Target/RISCVLateCodeGenTest.cpp
+++ b/backend/unittests/Target/RISCVLateCodeGenTest.cpp
@@ -1138,7 +1138,7 @@ void testCanonicalOptimizationPipelines(TestContext &Context,
SelectedPipeline.size() == 6,
"canonical selected-SSA optimization pipeline must register completely");
Context.expect(rcc::addPreRegisterAllocationOptimizationPipeline(PreRAPipeline, TargetInfo) &&
- PreRAPipeline.size() == 4,
+ PreRAPipeline.size() == 3,
"canonical pre-RA optimization pipeline must register completely");
auto Function = makeFunction(Context, "canonical_post_ra_pipeline", 21);
@@ -1180,7 +1180,7 @@ void testCanonicalOptimizationPipelines(TestContext &Context,
rcc::MachineFunctionPassManager Pipeline;
auto Added = rcc::addPostRegisterAllocationPipeline(Pipeline, TargetInfo);
- Context.expect(Added && Pipeline.size() == 20,
+ Context.expect(Added && Pipeline.size() == 19,
"canonical post-RA pipeline must register every required pass");
if (!Added)
return;