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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-17 03:04:21 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-17 03:04:21 +0800
commit9720e989ccdce77a2c45a8379d36ff4428e6c2bf (patch)
tree21e34dc243b118015bbd84c3adca5778807e1af9 /backend
parent45330a1806e9acfa84e9e8c0fbac6120118cf09e (diff)
downloadrcc-project-9720e989ccdce77a2c45a8379d36ff4428e6c2bf.tar.gz
rcc-project-9720e989ccdce77a2c45a8379d36ff4428e6c2bf.tar.xz
[RISCV][GlobalISel] Generate direct branch selection
Diffstat (limited to 'backend')
-rw-r--r--backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp13
-rw-r--r--backend/lib/Target/RISCV/RISCVGISelInteger.rccdesc10
2 files changed, 10 insertions, 13 deletions
diff --git a/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index cde2c8d..89b6ecd 100644
--- a/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -364,7 +364,6 @@ public:
case GenericOpcode::G_FPEXTLOAD:
case GenericOpcode::G_FPTRUNCSTORE:
case GenericOpcode::G_STORE:
- case GenericOpcode::G_BR:
case GenericOpcode::G_BRCOND:
return {};
case GenericOpcode::G_FCONSTANT: {
@@ -441,8 +440,6 @@ public:
return selectStore(Instruction, Function);
case GenericOpcode::G_FPTRUNCSTORE:
return selectFloatTruncStore(Instruction, Function, Target);
- case GenericOpcode::G_BR:
- return selectBranch(Instruction);
case GenericOpcode::G_BRCOND:
return selectConditionalBranch(Instruction);
case GenericOpcode::G_CONSTANT:
@@ -1425,16 +1422,6 @@ private:
return makeUnexpected(ErrorCode::Unsupported, "RISC-V cannot select this generic store type");
}
- [[nodiscard]] Expected<void> selectBranch(MachineInstr &Instruction) const {
- auto Zero = physicalRegister(PhysicalRegisterID::X0);
- if (!Zero)
- return std::unexpected(Zero.error());
- auto Inserted = insertPhysicalRegister(Instruction, 0, *Zero, RegisterOperandFlag::Define);
- if (!Inserted)
- return std::unexpected(Inserted.error());
- return Instruction.setOpcode(instructionOpcode(InstructionOpcode::JAL));
- }
-
[[nodiscard]] Expected<void> selectConditionalBranch(MachineInstr &Instruction) const {
auto Zero = physicalRegister(PhysicalRegisterID::X0);
if (!Zero)
diff --git a/backend/lib/Target/RISCV/RISCVGISelInteger.rccdesc b/backend/lib/Target/RISCV/RISCVGISelInteger.rccdesc
index f40e5d4..6ba88ef 100644
--- a/backend/lib/Target/RISCV/RISCVGISelInteger.rccdesc
+++ b/backend/lib/Target/RISCV/RISCVGISelInteger.rccdesc
@@ -1,5 +1,15 @@
selection_rules:
-
+ id: select_g_br
+ priority: 100
+ match:
+ opcode: G_BR
+ apply:
+ instructions:
+ - opcode: PseudoBR
+ root: true
+ operands: [{ operand: 0 }]
+ -
id: select_g_implicit_def
priority: 100
match: