[mubios] Configure PIIX PCI interrupt routing during POSTHEADmaster

PCI devices retained interrupt line zero, causing e1000 to request the
timer IRQ and fail to bring up the network interface.

Enumerate the root PCI bus, configure PIIX3 PIRQ A-D to IRQ10/10/11/11,
and assign device interrupt lines using the QEMU pc slot and pin mapping.
Keep the PIIX PM SCI on IRQ9 and configure level triggering in the ELCR
while preserving other IRQ settings.

Signed-off-by: Richard Qin <richard.qin.x@gmail.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/mubios/include/bios.h b/mubios/include/bios.h
index c52af80..3bd13dc 100644
--- a/mubios/include/bios.h
+++ b/mubios/include/bios.h
@@ -56,6 +56,7 @@ void kbd_init (void);
 void pic_init (void);
 void pit_init (void);
 void ioapic_init (void);
+void pci_irq_init (void);
 void vga_text_mode_init (void);
 
 void ivt_init (void);