diff options
| author | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 17:32:50 +0000 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 17:32:50 +0000 |
| commit | f29e711b76e7c6bb436111609fa0b14e5c448fb7 (patch) | |
| tree | 779b66de49904bca8d5cb0f76ae0e28f323bbe8b /proofsearch/include/atp/simplify | |
| parent | e8d3b8082110bd66c223ff053c48a8c65ab8da41 (diff) | |
| download | rcc-project-f29e711b76e7c6bb436111609fa0b14e5c448fb7.tar.gz rcc-project-f29e711b76e7c6bb436111609fa0b14e5c448fb7.tar.xz | |
refactor(core): address WB stage architectural and naming review feedback
- Renamed `wb_reg_write_data` and `wb_reg_write_addr` to `wb_rd_wdata` and `wb_rd_addr` respectively to comply with `docs/naming_convention.md`.
- Removed the 64-bit adder for `mem_wb_pc + 64'd4` from the WB stage to improve timing. Introduced a new `mem_wb_pc_plus_4` pipeline input instead.
- Added a `has_trap` signal to gate architectural state updates (`wb_reg_write_en` and `csr_req`) upon exceptions, ensuring precise exceptions without corrupting the register file or CSRs.
Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
Diffstat (limited to 'proofsearch/include/atp/simplify')
0 files changed, 0 insertions, 0 deletions