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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 04:11:58 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 04:11:58 +0800 |
| commit | 36ee7251fbb4350a5eee2549857e81291413e25d (patch) | |
| tree | c88d879b23f8a6566211f228ca724884cfaaa7a0 /rv64cpu/CMakeLists.txt | |
| parent | 78d024306458fd4f8df67feb53c37e78859a61c1 (diff) | |
| download | rcc-project-36ee7251fbb4350a5eee2549857e81291413e25d.tar.gz rcc-project-36ee7251fbb4350a5eee2549857e81291413e25d.tar.xz | |
build: reorganize CMake configuration
Diffstat (limited to 'rv64cpu/CMakeLists.txt')
| -rw-r--r-- | rv64cpu/CMakeLists.txt | 53 |
1 files changed, 11 insertions, 42 deletions
diff --git a/rv64cpu/CMakeLists.txt b/rv64cpu/CMakeLists.txt index da146d5..f16aa14 100644 --- a/rv64cpu/CMakeLists.txt +++ b/rv64cpu/CMakeLists.txt @@ -4,35 +4,22 @@ if(POLICY CMP0144) cmake_policy(SET CMP0144 NEW) endif() -project(richard_cpu +project(rv64cpu VERSION 0.1.0 - DESCRIPTION "RV64IMAZicsr_Zifencei Five-Stage Pipelined CPU SoC" - LANGUAGES CXX C + DESCRIPTION "RV64 RISC-V processor core written in SystemVerilog" + LANGUAGES CXX ) set(CMAKE_CXX_STANDARD 17) set(CMAKE_CXX_STANDARD_REQUIRED ON) set(CMAKE_EXPORT_COMPILE_COMMANDS ON) -# ─── Options ──────────────────────────────────────────────────────────────────── -option(ENABLE_TRACE "Enable VCD waveform tracing" ON) -option(ENABLE_COVERAGE "Enable code coverage for RTL" OFF) -option(BUILD_SW "Build software targets (requires riscv64 toolchain)" OFF) +option(ENABLE_TRACE "Enable VCD waveform tracing" OFF) +option(ENABLE_COVERAGE "Enable RTL code coverage" OFF) -# ─── Locate Verilator ──────────────────────────────────────────────────────────── find_package(verilator REQUIRED HINTS $ENV{VERILATOR_ROOT}) message(STATUS "Found Verilator: ${verilator_DIR}") -# ─── RTL Source Directories ────────────────────────────────────────────────────── -set(RTL_DIR ${CMAKE_SOURCE_DIR}/rtl) -set(RTL_CORE_DIR ${RTL_DIR}/core) -set(RTL_CACHE_DIR ${RTL_DIR}/cache) -set(RTL_BUS_DIR ${RTL_DIR}/bus) -set(RTL_PERIPS_DIR ${RTL_DIR}/perips) -set(RTL_SOC_DIR ${RTL_DIR}/soc) -set(RTL_INCLUDE_DIR ${RTL_CORE_DIR}/include) - -# ─── Common Verilator Flags ────────────────────────────────────────────────────── set(VERILATOR_COMMON_FLAGS --sv -Wall @@ -51,31 +38,13 @@ if(ENABLE_COVERAGE) list(APPEND VERILATOR_COMMON_FLAGS --coverage) endif() -# ─── Include Verilator CMake Helper ────────────────────────────────────────────── -include(${CMAKE_SOURCE_DIR}/tools/verilator.cmake) - -# ─── Waveform Output Directory ────────────────────────────────────────────────── -file(MAKE_DIRECTORY ${CMAKE_SOURCE_DIR}/waves) - -# ─── Testing ──────────────────────────────────────────────────────────────────── -enable_testing() -include(CTest) +include(${CMAKE_SOURCE_DIR}/cmake/verilator.cmake) -# ─── Testbench Subdirectory ───────────────────────────────────────────────────── -add_subdirectory(tb) - -# ─── Software Subdirectory (optional) ─────────────────────────────────────────── -if(BUILD_SW) - add_subdirectory(sw) -endif() +add_subdirectory(rtl) -# ─── Summary ──────────────────────────────────────────────────────────────────── message(STATUS "") -message(STATUS "╔══════════════════════════════════════════════╗") -message(STATUS "║ richard-cpu build configuration ║") -message(STATUS "╠══════════════════════════════════════════════╣") -message(STATUS "║ Trace: ${ENABLE_TRACE}") -message(STATUS "║ Coverage: ${ENABLE_COVERAGE}") -message(STATUS "║ Software: ${BUILD_SW}") -message(STATUS "╚══════════════════════════════════════════════╝") +message(STATUS "RV64CPU configuration") +message(STATUS " Trace: ${ENABLE_TRACE}") +message(STATUS " Coverage: ${ENABLE_COVERAGE}") +message(STATUS " RTL files: ${RV64CPU_RTL_SOURCE_COUNT}") message(STATUS "") |
