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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 04:31:31 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 04:31:31 +0800 |
| commit | a7d5b2468553c6d3570ca2aa45c27cb93e26cb88 (patch) | |
| tree | 7031b1fac52e4f858c4e92041485135242768f7b /rv64cpu/CMakeLists.txt | |
| parent | 4ca723bc9dc1b9db1bd03e3b3db0c58079c3f3c4 (diff) | |
| parent | 3b0b67af63af86c5ec9b2a63defa06b70923b2e3 (diff) | |
| download | rcc-project-a7d5b2468553c6d3570ca2aa45c27cb93e26cb88.tar.gz rcc-project-a7d5b2468553c6d3570ca2aa45c27cb93e26cb88.tar.xz | |
Merge remote-tracking branch 'rv64cpu-import/master'
Diffstat (limited to 'rv64cpu/CMakeLists.txt')
| -rw-r--r-- | rv64cpu/CMakeLists.txt | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/rv64cpu/CMakeLists.txt b/rv64cpu/CMakeLists.txt new file mode 100644 index 0000000..f16aa14 --- /dev/null +++ b/rv64cpu/CMakeLists.txt @@ -0,0 +1,50 @@ +cmake_minimum_required(VERSION 3.20) + +if(POLICY CMP0144) + cmake_policy(SET CMP0144 NEW) +endif() + +project(rv64cpu + VERSION 0.1.0 + DESCRIPTION "RV64 RISC-V processor core written in SystemVerilog" + LANGUAGES CXX +) + +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +option(ENABLE_TRACE "Enable VCD waveform tracing" OFF) +option(ENABLE_COVERAGE "Enable RTL code coverage" OFF) + +find_package(verilator REQUIRED HINTS $ENV{VERILATOR_ROOT}) +message(STATUS "Found Verilator: ${verilator_DIR}") + +set(VERILATOR_COMMON_FLAGS + --sv + -Wall + -Wno-DECLFILENAME + -Wno-UNUSED + --x-initial unique + --x-assign unique +) + +if(ENABLE_TRACE) + list(APPEND VERILATOR_COMMON_FLAGS --trace) + add_compile_definitions(VM_TRACE=1) +endif() + +if(ENABLE_COVERAGE) + list(APPEND VERILATOR_COMMON_FLAGS --coverage) +endif() + +include(${CMAKE_SOURCE_DIR}/cmake/verilator.cmake) + +add_subdirectory(rtl) + +message(STATUS "") +message(STATUS "RV64CPU configuration") +message(STATUS " Trace: ${ENABLE_TRACE}") +message(STATUS " Coverage: ${ENABLE_COVERAGE}") +message(STATUS " RTL files: ${RV64CPU_RTL_SOURCE_COUNT}") +message(STATUS "") |
