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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-04-01 05:11:48 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-04-01 05:11:48 +0800 |
| commit | def178f9df3819f01092400893651a148d529f2f (patch) | |
| tree | 00fe73e7ae3facdf98c836992c1489f77df87be5 /rv64cpu/README.md | |
| parent | be57ced99b660810158da4763e5a764ddefe3be1 (diff) | |
| download | rcc-project-def178f9df3819f01092400893651a148d529f2f.tar.gz rcc-project-def178f9df3819f01092400893651a148d529f2f.tar.xz | |
docs: update README and ISA support matrix with new dependencies and compliance status
Diffstat (limited to 'rv64cpu/README.md')
| -rw-r--r-- | rv64cpu/README.md | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/rv64cpu/README.md b/rv64cpu/README.md index e2b767d..72b3546 100644 --- a/rv64cpu/README.md +++ b/rv64cpu/README.md @@ -24,6 +24,9 @@ Written in SystemVerilog, simulated with Verilator, targeting official riscv-arc - CMake ≥ 3.20 - C++17 compiler (GCC / Clang) - [riscv64-unknown-elf-gcc](https://github.com/riscv-collab/riscv-gnu-toolchain) (software compilation, optional) +- [uv](https://docs.astral.sh/uv/) (ACT4 Python tooling) +- [podman](https://podman.io/) (riscv-unified-db runtime) +- [sail_riscv_sim 0.10](https://github.com/riscv/sail-riscv/releases/tag/0.10) (reference model for ACT4) - [GTKWave](http://gtkwave.sourceforge.net/) (waveform viewer, optional) ### Build Simulation @@ -54,10 +57,24 @@ cmake --build build_sw -j$(nproc) # Initialize riscv-arch-test submodule git submodule update --init --recursive -# Run RV64I test suite -python3 scripts/run_compliance.py --suite rv64i -v +# Sync ACT4 python dependencies +cd sw/riscv-arch-test && uv sync --frozen && cd ../.. + +# Run strict full implemented suite (reference signature compare enabled) +python3 scripts/run_compliance.py --suite rv64full --max-cycles 200000 --require-reference ``` +Verified strict suites (all pass): + +- `rv64i` +- `rv64im` +- `rv64ia` +- `rv64ic` +- `rv64if` +- `rv64id` +- `rv64priv` +- `rv64full` (aggregate) + ### View Waveforms ```bash @@ -111,12 +128,12 @@ richard-cpu/ | Phase | Milestone | |---|---| -| P1 | RV64I five-stage pipeline + hazard handling | -| P2 | CSR + M/S/U privilege levels + Trap | +| P1 | RV64I five-stage pipeline + hazard handling (Done) | +| P2 | CSR + M/S/U privilege levels + Trap (Done) | | P3 | MMU (Sv39 TLB + PTW) | | P4 | Cache + AXI4-Full Burst | | P5 | Peripherals + AXI4-Lite bridge + SoC integration | -| P6 | Pass riscv-arch-test | +| P6 | Pass riscv-arch-test (In Progress: strict suites above all pass) | | P7 | M/F/D/A/C extensions + FPGA bring-up | ## License |