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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 04:31:31 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 04:31:31 +0800 |
| commit | a7d5b2468553c6d3570ca2aa45c27cb93e26cb88 (patch) | |
| tree | 7031b1fac52e4f858c4e92041485135242768f7b /rv64cpu/cmake | |
| parent | 4ca723bc9dc1b9db1bd03e3b3db0c58079c3f3c4 (diff) | |
| parent | 3b0b67af63af86c5ec9b2a63defa06b70923b2e3 (diff) | |
| download | rcc-project-a7d5b2468553c6d3570ca2aa45c27cb93e26cb88.tar.gz rcc-project-a7d5b2468553c6d3570ca2aa45c27cb93e26cb88.tar.xz | |
Merge remote-tracking branch 'rv64cpu-import/master'
Diffstat (limited to 'rv64cpu/cmake')
| -rw-r--r-- | rv64cpu/cmake/verilator.cmake | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/rv64cpu/cmake/verilator.cmake b/rv64cpu/cmake/verilator.cmake new file mode 100644 index 0000000..8c0a006 --- /dev/null +++ b/rv64cpu/cmake/verilator.cmake @@ -0,0 +1,60 @@ +# ─── Verilator CMake Helper ────────────────────────────────────────────────────── +# +# Provides the `add_verilator_target()` function to simplify creating +# Verilator simulation executables. +# +# Usage: +# add_verilator_target( +# NAME tb_alu +# TOP_MODULE alu +# SOURCES ${RTL_CORE_DIR}/alu.sv +# INCLUDE_DIRS ${RTL_INCLUDE_DIR} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_alu.cpp +# PREFIX Valu +# ) + +function(add_verilator_target) + cmake_parse_arguments(VT + "" # Options + "NAME;TOP_MODULE;PREFIX" # Single-value args + "SOURCES;INCLUDE_DIRS;TB_SOURCES;EXTRA_FLAGS" # Multi-value args + ${ARGN} + ) + + if(NOT VT_PREFIX) + set(VT_PREFIX "V${VT_TOP_MODULE}") + endif() + + # Create C++ executable for the testbench + add_executable(${VT_NAME} ${VT_TB_SOURCES}) + + target_include_directories(${VT_NAME} PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/common + ) + + # Build include dir flags + set(_INCLUDE_FLAGS "") + foreach(_dir ${VT_INCLUDE_DIRS}) + list(APPEND _INCLUDE_FLAGS "-I${_dir}") + endforeach() + + # Verilate the RTL sources + verilate(${VT_NAME} + PREFIX ${VT_PREFIX} + SOURCES ${VT_SOURCES} + TOP_MODULE ${VT_TOP_MODULE} + VERILATOR_ARGS + ${VERILATOR_COMMON_FLAGS} + ${_INCLUDE_FLAGS} + ${VT_EXTRA_FLAGS} + ) + + # Register as CTest + add_test( + NAME ${VT_NAME} + COMMAND ${VT_NAME} + ) + + # Set test timeout + set_tests_properties(${VT_NAME} PROPERTIES TIMEOUT 60) +endfunction() |
