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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-04-01 05:11:48 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-04-01 05:11:48 +0800 |
| commit | def178f9df3819f01092400893651a148d529f2f (patch) | |
| tree | 00fe73e7ae3facdf98c836992c1489f77df87be5 /rv64cpu/docs | |
| parent | be57ced99b660810158da4763e5a764ddefe3be1 (diff) | |
| download | rcc-project-def178f9df3819f01092400893651a148d529f2f.tar.gz rcc-project-def178f9df3819f01092400893651a148d529f2f.tar.xz | |
docs: update README and ISA support matrix with new dependencies and compliance status
Diffstat (limited to 'rv64cpu/docs')
| -rw-r--r-- | rv64cpu/docs/isa_support.md | 40 |
1 files changed, 28 insertions, 12 deletions
diff --git a/rv64cpu/docs/isa_support.md b/rv64cpu/docs/isa_support.md index cf8c9c4..0173a58 100644 --- a/rv64cpu/docs/isa_support.md +++ b/rv64cpu/docs/isa_support.md @@ -14,22 +14,38 @@ Equivalent to `RV64IMAFDCZicsr_Zifencei` | Extension | Full Name | Status | Description | |---|---|---|---| -| **I** | Base Integer (RV64I) | 🟡 In progress | Five-stage RV64I pipeline, ALU, and branch unit implemented and covered by unit tests ([rtl/core/alu.sv](rtl/core/alu.sv), [tb/unit/tb_alu.cc](tb/unit/tb_alu.cc), [tb/unit/tb_branch.cc](tb/unit/tb_branch.cc)) | -| **M** | Multiply/Divide | 🔴 Not implemented | Multiply, divide, remainder | -| **A** | Atomic | 🔴 Not implemented | LR/SC, AMO atomic instructions | -| **F** | Single-Precision Float | 🔴 Not implemented | 32-bit IEEE 754 floating-point | -| **D** | Double-Precision Float | 🔴 Not implemented | 64-bit IEEE 754 floating-point | -| **C** | Compressed | 🔴 Not implemented | 16-bit compressed instructions | +| **I** | Base Integer (RV64I) | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64i`) | +| **M** | Multiply/Divide | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64im`) | +| **A** | Atomic | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64ia`) | +| **F** | Single-Precision Float | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64if`) | +| **D** | Double-Precision Float | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64id`) | +| **C** | Compressed | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64ic`) | | **Zicsr** | CSR Instructions | 🟢 Implemented | Full CSR unit with delegation, FCSR, and dedicated testbench ([rtl/core/csr_unit.sv](rtl/core/csr_unit.sv), [tb/unit/tb_csr.cc](tb/unit/tb_csr.cc)) | -| **Zifencei** | Instruction Fence | 🟡 Decoding only | Decoder recognizes FENCE.I; cache invalidation hookup pending | +| **Zifencei** | Instruction Fence | 🟢 Implemented | Included in strict ACT4 passing suites | ---- +Privilege-related tests (`S`, `Sm`) also pass through `rv64priv` strict suite. -## Recent Progress Highlights (2026-03) +--- -- **CSR subsystem**: `csr_unit` now handles delegation, privilege transitions, and floating-point CSRs, verified by [tb/unit/tb_csr.cc](tb/unit/tb_csr.cc). -- **Integer execution path**: ALU, branch, and decode paths for RV64I arithmetic/logic instructions are implemented with passing unit tests ([tb/unit/tb_alu.cc](tb/unit/tb_alu.cc), [tb/unit/tb_branch.cc](tb/unit/tb_branch.cc)). -- **Decoder coverage**: Load/store, immediate, and system opcode paths exist with clear TODO markers for upcoming M/A/F extensions, see [rtl/core/decoder.sv](rtl/core/decoder.sv). +## Recent Progress Highlights (2026-04) + +- `riscv-arch-test` ACT4 flow integrated in `scripts/run_compliance.py`. +- Dedicated `tb/compliance/compliance_runner.cc` executes ELF tests and dumps signatures. +- Strict suite passes with reference comparison enabled (`--require-reference`): + - `rv64i` (51/51) + - `rv64im` (64/64) + - `rv64ia` (51/51) + - `rv64ic` (51/51) + - `rv64if` (133/133) + - `rv64id` (165/165) + - `rv64priv` (2/2) + - `rv64full` aggregate (262/262) + +## Detailed Instruction Tables + +The detailed per-instruction checklist sections below are retained as reference, +but are not the primary source of truth for completion status at this stage. +Current completion is determined by strict ACT4 suite pass results listed above. --- |
