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authorRichard Qin <richard.qin.x@gmail.com>2026-03-17 21:23:51 +0800
committerRichard Qin <richard.qin.x@gmail.com>2026-03-17 21:23:51 +0800
commit4c18dcc24b7cef5b8ae7d2c86fac2be4bd48a5fe (patch)
tree7b3377a2823f69cdcf1078b92610e34b8e9e3533 /rv64cpu/rtl/core/decoder.sv
parent595c88dddaf4ddd14d0f24b2016a573fe96a6a02 (diff)
downloadrcc-project-4c18dcc24b7cef5b8ae7d2c86fac2be4bd48a5fe.tar.gz
rcc-project-4c18dcc24b7cef5b8ae7d2c86fac2be4bd48a5fe.tar.xz
fix known bugs
Diffstat (limited to 'rv64cpu/rtl/core/decoder.sv')
-rw-r--r--rv64cpu/rtl/core/decoder.sv2
1 files changed, 1 insertions, 1 deletions
diff --git a/rv64cpu/rtl/core/decoder.sv b/rv64cpu/rtl/core/decoder.sv
index 585a018..c948646 100644
--- a/rv64cpu/rtl/core/decoder.sv
+++ b/rv64cpu/rtl/core/decoder.sv
@@ -80,7 +80,7 @@ module decoder
assign opcode = instr[6:0];
assign rd_addr = instr[11:7];
assign funct3 = instr[14:12];
- assign rs1_addr = instr[19:15];
+ assign rs1_addr = (opcode == OPCODE_LUI) ? 5'b00000 : instr[19:15];
assign rs2_addr = instr[24:20];
assign funct7 = instr[31:25];