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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 21:23:51 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 21:23:51 +0800 |
| commit | 4c18dcc24b7cef5b8ae7d2c86fac2be4bd48a5fe (patch) | |
| tree | 7b3377a2823f69cdcf1078b92610e34b8e9e3533 /rv64cpu/rtl/core/ex_mem_reg.sv | |
| parent | 595c88dddaf4ddd14d0f24b2016a573fe96a6a02 (diff) | |
| download | rcc-project-4c18dcc24b7cef5b8ae7d2c86fac2be4bd48a5fe.tar.gz rcc-project-4c18dcc24b7cef5b8ae7d2c86fac2be4bd48a5fe.tar.xz | |
fix known bugs
Diffstat (limited to 'rv64cpu/rtl/core/ex_mem_reg.sv')
| -rw-r--r-- | rv64cpu/rtl/core/ex_mem_reg.sv | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/rv64cpu/rtl/core/ex_mem_reg.sv b/rv64cpu/rtl/core/ex_mem_reg.sv index 4fcf140..a8182aa 100644 --- a/rv64cpu/rtl/core/ex_mem_reg.sv +++ b/rv64cpu/rtl/core/ex_mem_reg.sv @@ -107,7 +107,7 @@ module ex_mem_reg ); always_ff @(posedge clk) begin - if (rst || flush_en) begin + if (rst) begin mem_alu_result <= '0; mem_branch_taken <= '0; mem_branch_target <= '0; @@ -138,6 +138,28 @@ module ex_mem_reg mem_is_fence <= '0; mem_is_fence_i <= '0; + end else if (flush_en) begin + // Critical control signals must be zeroed out + mem_branch_taken <= '0; + mem_is_load <= '0; + mem_is_store <= '0; + mem_mem_size <= '0; + mem_reg_write_en <= '0; + mem_rd_addr <= '0; + mem_wb_sel <= '0; + + // Exceptions and system control + mem_is_csr <= '0; + mem_csr_op <= '0; + mem_illegal_instr <= '0; + mem_is_ecall <= '0; + mem_is_ebreak <= '0; + mem_is_mret <= '0; + mem_is_sret <= '0; + mem_is_wfi <= '0; + mem_is_sfence_vma <= '0; + mem_is_fence <= '0; + mem_is_fence_i <= '0; end else if (~stall_en) begin mem_alu_result <= ex_alu_result; mem_branch_taken <= ex_branch_taken; |
