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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-03-18 01:15:41 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-03-18 01:15:41 +0800 |
| commit | c5ff16613608c91037274aee4d04d4f962eb1f57 (patch) | |
| tree | 61c0bef5b807090d4fc619ae1f744b034ff4b866 /rv64cpu/rtl/core/ex_mem_reg.sv | |
| parent | bd1d53990e8e7b94a2126682a3146de01a0c76ad (diff) | |
| parent | 35b7794d314295bd68b155c25950011a2f1cfcbc (diff) | |
| download | rcc-project-c5ff16613608c91037274aee4d04d4f962eb1f57.tar.gz rcc-project-c5ff16613608c91037274aee4d04d4f962eb1f57.tar.xz | |
Merge pull request #2 from Richard-Qin-001/audit-report-fixes-18055656287044378367
Finalized Richard CPU RTL Audit Report
Diffstat (limited to 'rv64cpu/rtl/core/ex_mem_reg.sv')
| -rw-r--r-- | rv64cpu/rtl/core/ex_mem_reg.sv | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/rv64cpu/rtl/core/ex_mem_reg.sv b/rv64cpu/rtl/core/ex_mem_reg.sv index a8182aa..2cc5e9e 100644 --- a/rv64cpu/rtl/core/ex_mem_reg.sv +++ b/rv64cpu/rtl/core/ex_mem_reg.sv @@ -37,7 +37,7 @@ module ex_mem_reg // ---------------------- // Bypassed Inputs from ID/EX Register - + // Data/Operands input logic [XLEN-1:0] ex_rs1_rdata, // Needed for CSRRW/RS/RC input logic [XLEN-1:0] ex_rs2_rdata, // Needed for store data @@ -116,7 +116,7 @@ module ex_mem_reg mem_rs1_addr <= '0; mem_pc <= '0; mem_imm <= '0; - + // Critical control signals must be zeroed out mem_is_load <= '0; mem_is_store <= '0; @@ -169,14 +169,14 @@ module ex_mem_reg mem_rs1_addr <= ex_rs1_addr; mem_pc <= ex_pc; mem_imm <= ex_imm; - + mem_is_load <= ex_is_load; mem_is_store <= ex_is_store; mem_mem_size <= ex_mem_size; mem_reg_write_en <= ex_reg_write_en; mem_rd_addr <= ex_rd_addr; mem_wb_sel <= ex_wb_sel; - + mem_is_csr <= ex_is_csr; mem_csr_op <= ex_csr_op; mem_illegal_instr <= ex_illegal_instr; |