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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 21:23:51 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 21:23:51 +0800 |
| commit | 4c18dcc24b7cef5b8ae7d2c86fac2be4bd48a5fe (patch) | |
| tree | 7b3377a2823f69cdcf1078b92610e34b8e9e3533 /rv64cpu/rtl/core/id_ex_reg.sv | |
| parent | 595c88dddaf4ddd14d0f24b2016a573fe96a6a02 (diff) | |
| download | rcc-project-4c18dcc24b7cef5b8ae7d2c86fac2be4bd48a5fe.tar.gz rcc-project-4c18dcc24b7cef5b8ae7d2c86fac2be4bd48a5fe.tar.xz | |
fix known bugs
Diffstat (limited to 'rv64cpu/rtl/core/id_ex_reg.sv')
| -rw-r--r-- | rv64cpu/rtl/core/id_ex_reg.sv | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/rv64cpu/rtl/core/id_ex_reg.sv b/rv64cpu/rtl/core/id_ex_reg.sv index 7c780ee..e88ce17 100644 --- a/rv64cpu/rtl/core/id_ex_reg.sv +++ b/rv64cpu/rtl/core/id_ex_reg.sv @@ -113,7 +113,7 @@ module id_ex_reg ); always_ff @(posedge clk) begin - if (rst || flush_en) begin + if (rst) begin ex_pc <= '0; ex_rs1_rdata <= '0; ex_rs2_rdata <= '0; @@ -144,6 +144,31 @@ module id_ex_reg ex_is_sfence_vma <= '0; ex_is_fence <= '0; ex_is_fence_i <= '0; + end else if (flush_en) begin + ex_alu_op <= ALU_ADD; // NOP is effectively ADD x0, x0, 0 + ex_alu_src1_sel <= '0; + ex_alu_src2_sel <= '0; + ex_is_word_op <= '0; + ex_is_branch <= '0; + ex_branch_op <= BRANCH_EQ; + ex_is_jump <= '0; + ex_is_load <= '0; + ex_is_store <= '0; + ex_mem_size <= '0; + ex_reg_write_en <= '0; // VERY IMPORTANT: Do not write to regfile on NOP + ex_rd_addr <= '0; + ex_wb_sel <= '0; + ex_is_csr <= '0; + ex_csr_op <= '0; + ex_illegal_instr <= '0; + ex_is_ecall <= '0; + ex_is_ebreak <= '0; + ex_is_mret <= '0; + ex_is_sret <= '0; + ex_is_wfi <= '0; + ex_is_sfence_vma <= '0; + ex_is_fence <= '0; + ex_is_fence_i <= '0; end else if (~stall_en) begin ex_pc <= id_pc; ex_rs1_rdata <= id_rs1_rdata; |
