Merge pull request #2 from Richard-Qin-001/audit-report-fixes-18055656287044378367

Finalized Richard CPU RTL Audit Report

1 files changed, 3 insertions, 3 deletions

diff --git a/rv64cpu/rtl/core/mem_wb_reg.sv b/rv64cpu/rtl/core/mem_wb_reg.sv
index eca60bc..a70057c 100644
--- a/rv64cpu/rtl/core/mem_wb_reg.sv
+++ b/rv64cpu/rtl/core/mem_wb_reg.sv
@@ -26,7 +26,7 @@ module mem_wb_reg
 
     // -----------------------
     // Control Signals from Hazard Unit
-    input  logic               stall_en,     
+    input  logic               stall_en,
     input  logic               flush_en,
 
     // -----------------------
@@ -53,7 +53,7 @@ module mem_wb_reg
     input  logic                   mem_is_ebreak,
     input  logic                   mem_is_mret,
     input  logic                   mem_is_sret,
-    
+
     // -----------------------
     // Outputs to WB Stage
     // -----------------------
@@ -78,7 +78,7 @@ module mem_wb_reg
     output logic                   wb_is_ebreak,
     output logic                   wb_is_mret,
     output logic                   wb_is_sret
-    
+
 );
     // Sequential Logic: State Update
     always_ff @(posedge clk) begin