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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-04-07 21:21:03 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-04-07 21:21:03 +0800 |
| commit | 328d4ef7537a98bab8f6891a0280cda9e03b0cee (patch) | |
| tree | a201ad9d62d2d566feb3da23d578e4df39f9a94a /rv64cpu/rtl/core/mmu | |
| parent | 9c34902e4a763109d7d6251781bcb92f6bc68c56 (diff) | |
| download | rcc-project-328d4ef7537a98bab8f6891a0280cda9e03b0cee.tar.gz rcc-project-328d4ef7537a98bab8f6891a0280cda9e03b0cee.tar.xz | |
feat(tlb): enhance TLB functionality with ASID-targeted flush and additional test cases
Diffstat (limited to 'rv64cpu/rtl/core/mmu')
| -rw-r--r-- | rv64cpu/rtl/core/mmu/tlb.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/rv64cpu/rtl/core/mmu/tlb.sv b/rv64cpu/rtl/core/mmu/tlb.sv index 521b08a..f466cb3 100644 --- a/rv64cpu/rtl/core/mmu/tlb.sv +++ b/rv64cpu/rtl/core/mmu/tlb.sv @@ -341,7 +341,7 @@ module tlb logic mode_match; logic [44:0] mask; - asid_match = !flush_asid_valid || entries[i].g || (entries[i].asid == flush_asid); + asid_match = !flush_asid_valid || (!entries[i].g && (entries[i].asid == flush_asid)); mode_match = !flush_vpn_valid || (entries[i].mode == flush_mode); if (flush_vpn_valid) begin mask = make_vpn_mask(entries[i].mode, entries[i].level); |