fix naming problems

3 files changed, 39 insertions, 39 deletions

diff --git a/rv64cpu/rtl/core/alu.sv b/rv64cpu/rtl/core/alu.sv
index ac2e9c9..abfc238 100644
--- a/rv64cpu/rtl/core/alu.sv
+++ b/rv64cpu/rtl/core/alu.sv
@@ -21,44 +21,44 @@ module alu
     import rv64_pkg::*;
 (
     input  alu_op_t          alu_op,     // ALU operation select (from decoder)
-    input  logic [XLEN-1:0]  rs1_val,    // Operand 1 (register rs1 value or PC)
-    input  logic [XLEN-1:0]  rs2_val,    // Operand 2 (register rs2 value or immediate)
+    input  logic [XLEN-1:0]  operand_a,    // Operand 1 (register rs1 value or PC)
+    input  logic [XLEN-1:0]  operand_b,    // Operand 2 (register rs2 value or immediate)
 
-    output logic [XLEN-1:0]  alu_res     // ALU result
+    output logic [XLEN-1:0]  alu_result     // ALU result
 );
 
     // Shift amount: RV64I uses lower 6 bits of rs2 (shamt[5:0])
     logic [5:0] shamt;
-    assign shamt = rs2_val[5:0];
+    assign shamt = operand_b[5:0];
 
     always_comb begin
-        alu_res = '0;
+        alu_result = '0;
 
         case (alu_op)
-            ALU_ADD:  alu_res = rs1_val + rs2_val;
-            ALU_SUB:  alu_res = rs1_val - rs2_val;
+            ALU_ADD:  alu_result = operand_a + operand_b;
+            ALU_SUB:  alu_result = operand_a - operand_b;
 
             // Logical left shift: the shift amount is the lower 6 bits of rs2
-            ALU_SLL:  alu_res = rs1_val << shamt;
+            ALU_SLL:  alu_result = operand_a << shamt;
 
             // Set less than (signed)
-            ALU_SLT:  alu_res = {63'b0, $signed(rs1_val) < $signed(rs2_val)};
+            ALU_SLT:  alu_result = {63'b0, $signed(operand_a) < $signed(operand_b)};
 
             // Set less than (unsigned)
-            ALU_SLTU: alu_res = {63'b0, rs1_val < rs2_val};
+            ALU_SLTU: alu_result = {63'b0, operand_a < operand_b};
 
-            ALU_XOR:  alu_res = rs1_val ^ rs2_val;
+            ALU_XOR:  alu_result = operand_a ^ operand_b;
 
             // Logical right shift: the shift amount is the lower 6 bits of rs2
-            ALU_SRL:  alu_res = rs1_val >> shamt;
+            ALU_SRL:  alu_result = operand_a >> shamt;
 
             // Arithmetic right shift: the shift amount is the lower 6 bits of rs2
-            ALU_SRA:  alu_res = $unsigned($signed(rs1_val) >>> shamt);
+            ALU_SRA:  alu_result = $unsigned($signed(operand_a) >>> shamt);
 
-            ALU_OR:   alu_res = rs1_val | rs2_val;
-            ALU_AND:  alu_res = rs1_val & rs2_val;
+            ALU_OR:   alu_result = operand_a | operand_b;
+            ALU_AND:  alu_result = operand_a & operand_b;
 
-            default:  alu_res = '0;
+            default:  alu_result = '0;
         endcase
     end
 
diff --git a/rv64cpu/rtl/core/decoder.sv b/rv64cpu/rtl/core/decoder.sv
index 8f35c47..585a018 100644
--- a/rv64cpu/rtl/core/decoder.sv
+++ b/rv64cpu/rtl/core/decoder.sv
@@ -28,7 +28,7 @@ module decoder
     output logic [4:0]        rs1_addr,       // Source register 1 address
     output logic [4:0]        rs2_addr,       // Source register 2 address
     output logic [4:0]        rd_addr,        // Destination register address
-    output logic              reg_write,      // Register file write enable
+    output logic              reg_write_en,      // Register file write enable
 
     // ALU Control
     output alu_op_t           alu_op,         // ALU operation select
@@ -112,7 +112,7 @@ module decoder
         alu_op        = ALU_ADD;
         alu_src1_sel  = 1'b0;   // rs1
         alu_src2_sel  = 1'b0;   // rs2
-        reg_write     = 1'b0;
+        reg_write_en  = 1'b0;
         imm           = '0;
         is_load       = 1'b0;
         is_store      = 1'b0;
@@ -139,7 +139,7 @@ module decoder
             // LUI — rd = imm_u
 
             OPCODE_LUI: begin
-                reg_write    = 1'b1;
+                reg_write_en = 1'b1;
                 alu_src1_sel = 1'b0;    // doesn't matter,  ALU_ADD(0, imm_u)
                 alu_src2_sel = 1'b1;    // immediate
                 imm          = imm_u;
@@ -153,7 +153,7 @@ module decoder
 
 
             OPCODE_AUIPC: begin
-                reg_write    = 1'b1;
+                reg_write_en = 1'b1;
                 alu_src1_sel = 1'b1;    // PC
                 alu_src2_sel = 1'b1;    // immediate
                 imm          = imm_u;
@@ -163,7 +163,7 @@ module decoder
             // -----------------
             // JAL — rd = PC+4;  PC = PC + imm_j
             OPCODE_JAL: begin
-                reg_write    = 1'b1;
+                reg_write_en = 1'b1;
                 is_jump      = 1'b1;
                 alu_src1_sel = 1'b1;    // PC
                 alu_src2_sel = 1'b1;    // immediate
@@ -176,7 +176,7 @@ module decoder
             // JALR — rd = PC+4;  PC = (rs1 + imm_i) & ~1
 
             OPCODE_JALR: begin
-                reg_write    = 1'b1;
+                reg_write_en = 1'b1;
                 is_jump      = 1'b1;
                 alu_src1_sel = 1'b0;    // rs1
                 alu_src2_sel = 1'b1;    // immediate
@@ -188,7 +188,7 @@ module decoder
             // -----------------
             // Branch — compare rs1, rs2;  if taken, PC = PC + imm_b
             OPCODE_BRANCH: begin
-                reg_write    = 1'b0;    // branches never write rd
+                reg_write_en = 1'b0;    // branches never write rd
                 is_branch    = 1'b1;
                 alu_src1_sel = 1'b1;    // PC  (ALU computes branch target)
                 alu_src2_sel = 1'b1;    // immediate
@@ -200,7 +200,7 @@ module decoder
             // -----------------
             // Load — rd = Mem[rs1 + imm_i]
             OPCODE_LOAD: begin
-                reg_write    = 1'b1;
+                reg_write_en = 1'b1;
                 is_load      = 1'b1;
                 alu_src1_sel = 1'b0;    // rs1
                 alu_src2_sel = 1'b1;    // immediate
@@ -213,7 +213,7 @@ module decoder
             // -----------------
             // Store — Mem[rs1 + imm_s] = rs2
             OPCODE_STORE: begin
-                reg_write    = 1'b0;
+                reg_write_en = 1'b0;
                 is_store     = 1'b1;
                 alu_src1_sel = 1'b0;    // rs1
                 alu_src2_sel = 1'b1;    // immediate  (NOT rs2 — rs2 is store data)
@@ -226,7 +226,7 @@ module decoder
             // OP-IMM (I-type ALU) — rd = rs1 OP imm
             // ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
             OPCODE_OP_IMM: begin
-                reg_write    = 1'b1;
+                reg_write_en = 1'b1;
                 alu_src1_sel = 1'b0;    // rs1
                 alu_src2_sel = 1'b1;    // immediate
                 imm          = imm_i;
@@ -248,7 +248,7 @@ module decoder
             // OP-IMM-32 (I-type ALU, 32-bit word variants for RV64)
             // ADDIW, SLLIW, SRLIW, SRAIW
             OPCODE_OP_IMM_32: begin
-                reg_write    = 1'b1;
+                reg_write_en = 1'b1;
                 is_word_op   = 1'b1;    // EX stage: operate on lower 32 bits, sext result
                 alu_src1_sel = 1'b0;    // rs1
                 alu_src2_sel = 1'b1;    // immediate
@@ -269,7 +269,7 @@ module decoder
             // OP (R-type ALU) — rd = rs1 OP rs2
             // ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
             OPCODE_OP: begin
-                reg_write    = 1'b1;
+                reg_write_en = 1'b1;
                 alu_src1_sel = 1'b0;    // rs1
                 alu_src2_sel = 1'b0;    // rs2
 
@@ -296,7 +296,7 @@ module decoder
             // OP-32 (R-type ALU, 32-bit word variants for RV64)
             // ADDW, SUBW, SLLW, SRLW, SRAW
             OPCODE_OP_32: begin
-                reg_write    = 1'b1;
+                reg_write_en = 1'b1;
                 is_word_op   = 1'b1;
                 alu_src1_sel = 1'b0;    // rs1
                 alu_src2_sel = 1'b0;    // rs2
@@ -333,7 +333,7 @@ module decoder
             OPCODE_SYSTEM: begin
                 if (funct3 == 3'b000) begin
                     // Privileged instructions (non-CSR)
-                    reg_write = 1'b0;
+                    reg_write_en = 1'b0;
                     case ({funct7, instr[24:20]})    // {funct7, rs2}
                         12'b0000000_00000: is_ecall      = 1'b1;   // ECALL
                         12'b0000000_00001: is_ebreak     = 1'b1;   // EBREAK
@@ -351,7 +351,7 @@ module decoder
                     // CSR instructions
                     // funct3: 001=CSRRW, 010=CSRRS, 011=CSRRC,
                     //         101=CSRRWI, 110=CSRRSI, 111=CSRRCI
-                    reg_write    = 1'b1;
+                    reg_write_en = 1'b1;
                     is_csr       = 1'b1;
                     csr_op       = funct3;
                     imm          = imm_i;   // CSR address = instr[31:20] (reuse imm_i path)
diff --git a/rv64cpu/rtl/core/regfile.sv b/rv64cpu/rtl/core/regfile.sv
index 83e09b7..640890d 100644
--- a/rv64cpu/rtl/core/regfile.sv
+++ b/rv64cpu/rtl/core/regfile.sv
@@ -25,24 +25,24 @@ module regfile
 
     // Read port 1
     input  logic [4:0]                rs1_addr, // Read address 1
-    output logic [XLEN-1:0]           rs1_val,  // Read data 1
+    output logic [XLEN-1:0]           rs1_rdata,  // Read data 1
 
     // Read port 2
     input  logic [4:0]                rs2_addr, // Read address 2
-    output logic [XLEN-1:0]           rs2_val,  // Read data 2
+    output logic [XLEN-1:0]           rs2_rdata,  // Read data 2
 
     // Write port
     input  logic [4:0]                rd_addr,  // Write address
-    input  logic [XLEN-1:0]           rd_val,   // Write data
-    input  logic                      we        // Write enable signal
+    input  logic [XLEN-1:0]           rd_wdata,   // Write data
+    input  logic                      reg_write_en // Write enable signal
 );
 
     // Register file storage
     logic [XLEN-1:0] regs [0:31];
 
     // Read Logic (combinational logic)
-    assign rs1_val = (rs1_addr == 5'b0) ? '0 : regs[rs1_addr];
-    assign rs2_val = (rs2_addr == 5'b0) ? '0 : regs[rs2_addr];
+    assign rs1_rdata = (rs1_addr == 5'b0) ? '0 : regs[rs1_addr];
+    assign rs2_rdata = (rs2_addr == 5'b0) ? '0 : regs[rs2_addr];
 
     // Write Logic (sequential logic)
     always_ff @(posedge clk) begin
@@ -51,8 +51,8 @@ module regfile
                 regs[i] <= '0;
             end
         end else begin
-            if (we && rd_addr != 5'b0) begin
-                regs[rd_addr] <= rd_val;
+            if (reg_write_en && rd_addr != 5'b0) begin
+                regs[rd_addr] <= rd_wdata;
             end
         end
     end