feat: Complete CSR/privileged/exception interrupt path and fill in strict acceptance tests

- Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process
- Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return
- Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios
- Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers
- Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case
- Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc.
- Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite

Verification:

- Build passed
- Full CTest passed (22/22)

11 files changed, 410 insertions, 135 deletions

diff --git a/rv64cpu/rtl/core/csr_unit.sv b/rv64cpu/rtl/core/csr_unit.sv
index 1749790..0427eeb 100644
--- a/rv64cpu/rtl/core/csr_unit.sv
+++ b/rv64cpu/rtl/core/csr_unit.sv
@@ -32,12 +32,13 @@ module csr_unit
 	input  logic [2:0]        csr_op,
 	input  logic [11:0]       csr_addr,
 	input  logic [XLEN-1:0]   csr_rs1_data,
-	input  logic              trap_illegal_instr,
-	input  logic              trap_is_ecall,
-	input  logic              trap_is_ebreak,
-	input  logic              trap_is_mret,
-	input  logic              trap_is_sret,
-	input  logic [XLEN-1:0]   trap_epc,
+	input  logic              trap_ctrl_trigger,
+	input  logic              trap_ctrl_to_s_mode,
+	input  logic [XLEN-1:0]   trap_ctrl_mepc,
+	input  logic [XLEN-1:0]   trap_ctrl_mcause,
+	input  logic [XLEN-1:0]   trap_ctrl_mtval,
+	input  logic              trap_ctrl_mret_en,
+	input  logic              trap_ctrl_sret_en,
 	output logic [XLEN-1:0]   csr_rdata,
 	output logic [XLEN-1:0]   csr_mstatus,
 	output logic [XLEN-1:0]   csr_sstatus,
@@ -51,6 +52,8 @@ module csr_unit
 	output logic [1:0]        csr_priv_mode,
 	output logic [XLEN-1:0]   csr_trap_vector,
 	output logic              csr_trap_to_s_mode,
+	output logic [XLEN-1:0]   csr_trap_vector_next,
+	output logic              csr_trap_to_s_mode_next,
 	output logic              csr_illegal_access
 );
 
@@ -110,16 +113,17 @@ module csr_unit
 	logic            is_clear_cmd;
 	logic            has_non_zero_data;
 	logic            csr_write_en;
-	logic            trap_event;
-	logic [5:0]      trap_cause_index;
-	logic            trap_delegated_to_s;
-	logic [XLEN-1:0] trap_cause_value;
 	logic [XLEN-1:0] trap_vector_target;
-	logic [XLEN-1:0] trap_vector_q;
 	logic            csr_addr_supported;
 	logic            csr_write_illegal;
 	logic [XLEN-1:0] csr_read_data;
+	logic [XLEN-1:0] trap_vector_q;
 	logic            trap_to_s_q;
+	logic            trap_taken;
+	logic            trap_taken_to_s_mode;
+	logic [XLEN-1:0] trap_taken_mepc;
+	logic [XLEN-1:0] trap_taken_mcause;
+	logic [XLEN-1:0] trap_taken_mtval;
 
 	// Canonicalize addresses, decode operations, and prepare CSR/trap metadata.
 	assign csr_addr_canonical = canonical_addr(csr_addr);
@@ -129,27 +133,31 @@ module csr_unit
 	assign has_non_zero_data  = |csr_rs1_data;
 	assign csr_addr_supported = csr_is_supported(csr_addr_canonical);
 	assign csr_write_en       = csr_req & csr_addr_supported & (is_write_cmd | ((is_set_cmd | is_clear_cmd) & has_non_zero_data));
-	assign trap_event         = trap_illegal_instr | trap_is_ecall | trap_is_ebreak;
-	assign trap_cause_value   = compute_trap_cause(priv_mode_q, trap_illegal_instr, trap_is_ecall, trap_is_ebreak);
-	assign trap_cause_index   = trap_cause_value[5:0];
-	assign trap_delegated_to_s = trap_event && (priv_mode_q != PRIV_MODE_M) && medeleg_reg[trap_cause_index];
-	assign trap_vector_target = trap_delegated_to_s ? stvec_reg : mtvec_reg;
-	assign csr_read_data      = read_csr(csr_addr_canonical);
-	assign csr_rdata          = csr_read_data;
-	assign csr_mstatus        = mstatus_reg;
-	assign csr_sstatus        = sstatus_reg;
-	assign csr_medeleg        = medeleg_reg;
-	assign csr_mideleg        = mideleg_reg;
-	assign csr_mtvec          = mtvec_reg;
-	assign csr_stvec          = stvec_reg;
-	assign csr_mepc           = mepc_reg;
-	assign csr_sepc           = sepc_reg;
-	assign csr_satp           = satp_reg;
-	assign csr_priv_mode      = priv_mode_q;
-	assign csr_trap_vector    = trap_vector_q;
-	assign csr_trap_to_s_mode = trap_to_s_q;
-	assign csr_write_illegal  = (csr_req && (is_write_cmd || is_set_cmd || is_clear_cmd) && !csr_is_writable(csr_addr_canonical));
-	assign csr_illegal_access = csr_req && (!csr_addr_supported || csr_write_illegal);
+	assign trap_taken               = trap_ctrl_trigger;
+	assign trap_taken_to_s_mode     = trap_ctrl_to_s_mode;
+	assign trap_taken_mepc          = trap_ctrl_mepc;
+	assign trap_taken_mcause        = trap_ctrl_mcause;
+	assign trap_taken_mtval         = trap_ctrl_mtval;
+
+	assign trap_vector_target      = trap_taken_to_s_mode ? stvec_reg : mtvec_reg;
+	assign csr_read_data           = read_csr(csr_addr_canonical);
+	assign csr_rdata               = csr_read_data;
+	assign csr_mstatus             = mstatus_reg;
+	assign csr_sstatus             = sstatus_reg;
+	assign csr_medeleg             = medeleg_reg;
+	assign csr_mideleg             = mideleg_reg;
+	assign csr_mtvec               = mtvec_reg;
+	assign csr_stvec               = stvec_reg;
+	assign csr_mepc                = mepc_reg;
+	assign csr_sepc                = sepc_reg;
+	assign csr_satp                = satp_reg;
+	assign csr_priv_mode           = priv_mode_q;
+	assign csr_trap_vector         = trap_vector_q;
+	assign csr_trap_to_s_mode      = trap_to_s_q;
+	assign csr_trap_vector_next    = trap_vector_target;
+	assign csr_trap_to_s_mode_next = trap_taken_to_s_mode;
+	assign csr_write_illegal       = (csr_req && (is_write_cmd || is_set_cmd || is_clear_cmd) && !csr_is_writable(csr_addr_canonical));
+	assign csr_illegal_access      = csr_req && (!csr_addr_supported || csr_write_illegal);
 
 	// Main CSR state machine: counts cycles, processes CSR writes, and reacts to traps/returns.
 	always_ff @(posedge clk) begin
@@ -186,7 +194,7 @@ module csr_unit
 		end else begin
 			mcycle_reg <= mcycle_reg + 64'd1;
 			time_reg   <= time_reg + 64'd1;
-			if (!trap_event) begin
+			if (!trap_taken) begin
 				minstret_reg <= minstret_reg + 64'd1;
 			end
 
@@ -245,11 +253,11 @@ module csr_unit
 				endcase
 			end
 
-			if (trap_event) begin
+			if (trap_taken) begin
 				trap_vector_q <= trap_vector_target;
-				trap_to_s_q   <= trap_delegated_to_s;
+				trap_to_s_q   <= trap_taken_to_s_mode;
 				// Update privilege-specific CSRs based on whether the trap was delegated.
-				if (trap_delegated_to_s) begin
+				if (trap_taken_to_s_mode) begin
 					logic [XLEN-1:0] next_sstatus;
 					next_sstatus = sstatus_reg;
 					next_sstatus[SSTATUS_SPIE_BIT] = sstatus_reg[SSTATUS_SIE_BIT];
@@ -257,9 +265,9 @@ module csr_unit
 					next_sstatus[SSTATUS_SPP_BIT]  = (priv_mode_q == PRIV_MODE_S);
 					sstatus_reg <= next_sstatus;
 					mstatus_reg <= apply_sstatus_to_mstatus(mstatus_reg, next_sstatus);
-					sepc_reg    <= trap_epc;
-					scause_reg  <= trap_cause_value;
-					stval_reg   <= trap_illegal_instr ? trap_epc : '0;
+					sepc_reg    <= trap_taken_mepc;
+					scause_reg  <= trap_taken_mcause;
+					stval_reg   <= trap_taken_mtval;
 					priv_mode_q <= PRIV_MODE_S;
 				end else begin
 					logic [XLEN-1:0] next_mstatus;
@@ -269,13 +277,13 @@ module csr_unit
 					next_mstatus[MSTATUS_MPP_HI:MSTATUS_MPP_LO] = encode_priv_mode(priv_mode_q);
 					mstatus_reg <= next_mstatus;
 					sstatus_reg <= mirror_mstatus_to_sstatus(sstatus_reg, next_mstatus);
-					mepc_reg    <= trap_epc;
-					mcause_reg  <= trap_cause_value;
-					mtval_reg   <= trap_illegal_instr ? trap_epc : '0;
+					mepc_reg    <= trap_taken_mepc;
+					mcause_reg  <= trap_taken_mcause;
+					mtval_reg   <= trap_taken_mtval;
 					priv_mode_q <= PRIV_MODE_M;
 				end
 			end else begin
-				if (trap_is_mret) begin
+				if (trap_ctrl_mret_en) begin
 					priv_mode_t return_mode;
 					logic [XLEN-1:0] next_mstatus;
 					return_mode  = decode_priv_mode(mstatus_reg[MSTATUS_MPP_HI:MSTATUS_MPP_LO]);
@@ -288,7 +296,7 @@ module csr_unit
 					priv_mode_q <= return_mode;
 				end
 
-				if (trap_is_sret) begin
+				if (trap_ctrl_sret_en) begin
 					logic [XLEN-1:0] next_sstatus;
 					next_sstatus = sstatus_reg;
 					next_sstatus[SSTATUS_SIE_BIT]  = sstatus_reg[SSTATUS_SPIE_BIT];
@@ -432,28 +440,6 @@ module csr_unit
 		endcase
 	endfunction
 
-	function automatic logic [XLEN-1:0] compute_trap_cause(
-		input priv_mode_t mode,
-		input logic       illegal_instr,
-		input logic       is_ecall,
-		input logic       is_ebreak
-	);
-		logic [XLEN-1:0] cause_val;
-		cause_val = '0;
-		if (illegal_instr) begin
-			cause_val = EXC_INST_ILLEGAL;
-		end else if (is_ebreak) begin
-			cause_val = EXC_BREAKPOINT;
-		end else if (is_ecall) begin
-			case (mode)
-				PRIV_MODE_U: cause_val = EXC_ECALL_FROM_U;
-				PRIV_MODE_S: cause_val = EXC_ECALL_FROM_S;
-				default:     cause_val = EXC_ECALL_FROM_M;
-			endcase
-		end
-		return cause_val;
-	endfunction
-
 	function automatic logic [XLEN-1:0] read_csr(input logic [11:0] addr);
 		logic [XLEN-1:0] data_out;
 		unique case (addr)
diff --git a/rv64cpu/rtl/core/decoder.sv b/rv64cpu/rtl/core/decoder.sv
index c948646..8e5e18f 100644
--- a/rv64cpu/rtl/core/decoder.sv
+++ b/rv64cpu/rtl/core/decoder.sv
@@ -23,6 +23,7 @@ module decoder
     import rv64_pkg::*;
 (
     input  logic [31:0]       instr,          // 32-bit instruction
+    input  logic [1:0]        priv_mode,      // Current privilege mode from CSR
 
     // Register File
     output logic [4:0]        rs1_addr,       // Source register 1 address
@@ -73,6 +74,12 @@ module decoder
     // ============================
     // Instruction Field Extraction
     // ============================
+    typedef enum logic [1:0] {
+        PRIV_MODE_U = 2'b00,
+        PRIV_MODE_S = 2'b01,
+        PRIV_MODE_M = 2'b11
+    } priv_mode_t;
+
     logic [6:0] opcode;
     logic [2:0] funct3;
     logic [6:0] funct7;
@@ -88,6 +95,7 @@ module decoder
     // Immediate Generation
     // ============================
     logic [XLEN-1:0] imm_i, imm_s, imm_b, imm_u, imm_j;
+    logic [11:0]     csr_addr_field;
 
     // I-type:  instr[31:20]
     assign imm_i = {{52{instr[31]}}, instr[31:20]};
@@ -103,6 +111,26 @@ module decoder
 
     // J-type:  {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}
     assign imm_j = {{43{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
+    assign csr_addr_field = instr[31:20];
+
+    function automatic int priv_rank(logic [1:0] mode);
+        case (mode)
+            PRIV_MODE_U: return 0;
+            PRIV_MODE_S: return 1;
+            2'b10:       return 2; // Reserved/H-mode, treat as higher than S
+            default:     return 3; // Machine mode (or anything else) highest
+        endcase
+    endfunction
+
+    function automatic logic priv_ge(logic [1:0] cur, logic [1:0] req);
+        return priv_rank(cur) >= priv_rank(req);
+    endfunction
+
+    function automatic logic csr_access_allowed(logic [1:0] cur, logic [11:0] addr);
+        logic [1:0] req_priv;
+        req_priv = addr[9:8];
+        return priv_ge(cur, req_priv);
+    endfunction
 
     // ============================
     // Main Decode Logic
@@ -337,14 +365,28 @@ module decoder
                     case ({funct7, instr[24:20]})    // {funct7, rs2}
                         12'b0000000_00000: is_ecall      = 1'b1;   // ECALL
                         12'b0000000_00001: is_ebreak     = 1'b1;   // EBREAK
-                        12'b0011000_00010: is_mret       = 1'b1;   // MRET
-                        12'b0001000_00010: is_sret       = 1'b1;   // SRET
+                        12'b0011000_00010: begin                  // MRET
+                            if (priv_mode == PRIV_MODE_M)
+                                is_mret = 1'b1;
+                            else
+                                illegal_instr = 1'b1;
+                        end
+                        12'b0001000_00010: begin                  // SRET
+                            if (priv_ge(priv_mode, PRIV_MODE_S))
+                                is_sret = 1'b1;
+                            else
+                                illegal_instr = 1'b1;
+                        end
                         12'b0001000_00101: is_wfi        = 1'b1;   // WFI
                         default: begin
-                            if (funct7 == 7'b0001001)
-                                is_sfence_vma = 1'b1;              // SFENCE.VMA
-                            else
+                            if (funct7 == 7'b0001001) begin
+                                if (priv_ge(priv_mode, PRIV_MODE_S))
+                                    is_sfence_vma = 1'b1;           // SFENCE.VMA
+                                else
+                                    illegal_instr = 1'b1;
+                            end else begin
                                 illegal_instr = 1'b1;
+                            end
                         end
                     endcase
                 end else begin
@@ -355,6 +397,11 @@ module decoder
                     is_csr       = 1'b1;
                     csr_op       = funct3;
                     imm          = imm_i;   // CSR address = instr[31:20] (reuse imm_i path)
+                    if (!csr_access_allowed(priv_mode, csr_addr_field)) begin
+                        reg_write_en  = 1'b0;
+                        is_csr        = 1'b0;
+                        illegal_instr = 1'b1;
+                    end
                 end
             end
 
diff --git a/rv64cpu/rtl/core/ex_mem_reg.sv b/rv64cpu/rtl/core/ex_mem_reg.sv
index 2cc5e9e..783dced 100644
--- a/rv64cpu/rtl/core/ex_mem_reg.sv
+++ b/rv64cpu/rtl/core/ex_mem_reg.sv
@@ -44,6 +44,7 @@ module ex_mem_reg
     input  logic [4:0]             ex_rs1_addr,   // Serves as zimm for CSRRWI/SI/CI
     input  logic [XLEN-1:0]        ex_pc,         // PC passed along for exceptions/CSRs
     input  logic [XLEN-1:0]        ex_imm,        // Imm passed for CSR writes
+    input  logic [INST_WIDTH-1:0]  ex_instr,
 
     // Memory Control
     input  logic                   ex_is_load,
@@ -81,6 +82,7 @@ module ex_mem_reg
     output logic [4:0]             mem_rs1_addr,
     output logic [XLEN-1:0]        mem_pc,
     output logic [XLEN-1:0]        mem_imm,
+    output logic [INST_WIDTH-1:0]  mem_instr,
 
     // Memory Control
     output logic                   mem_is_load,
@@ -108,6 +110,7 @@ module ex_mem_reg
 
     always_ff @(posedge clk) begin
         if (rst) begin
+            mem_instr        <= '0;
             mem_alu_result    <= '0;
             mem_branch_taken  <= '0;
             mem_branch_target <= '0;
@@ -139,6 +142,7 @@ module ex_mem_reg
             mem_is_fence_i    <= '0;
 
         end else if (flush_en) begin
+            mem_instr        <= '0;
             // Critical control signals must be zeroed out
             mem_branch_taken  <= '0;
             mem_is_load       <= '0;
@@ -169,6 +173,7 @@ module ex_mem_reg
              mem_rs1_addr      <= ex_rs1_addr;
              mem_pc            <= ex_pc;
              mem_imm           <= ex_imm;
+             mem_instr         <= ex_instr;
 
              mem_is_load       <= ex_is_load;
              mem_is_store      <= ex_is_store;
diff --git a/rv64cpu/rtl/core/hazard_unit.sv b/rv64cpu/rtl/core/hazard_unit.sv
index 2798116..aef550c 100644
--- a/rv64cpu/rtl/core/hazard_unit.sv
+++ b/rv64cpu/rtl/core/hazard_unit.sv
@@ -37,6 +37,7 @@ module hazard_unit
     input  logic        ex_reg_write_en,
     input  logic        ex_is_load,
     input  logic        ex_branch_taken,
+    input  logic [XLEN-1:0] ex_branch_target,
 
     // -----------------------
     // Inputs from MEM Stage (EX/MEM register outputs)
@@ -46,6 +47,13 @@ module hazard_unit
     input  logic        mem_stall_req,       // D-Cache miss or memory busy
 
     // -----------------------
+    // Trap Controller Inputs
+    // -----------------------
+    input  logic        trap_flush_req,
+    input  logic        trap_pc_sel,
+    input  logic [XLEN-1:0] trap_target_pc,
+
+    // -----------------------
     // Inputs from WB Stage (MEM/WB register outputs)
     // -----------------------
     input  logic [4:0]  wb_rd_addr,
@@ -66,7 +74,14 @@ module hazard_unit
     output logic        id_ex_stall_en,
     output logic        ex_mem_stall_en,
     output logic        if_id_flush_en,
-    output logic        id_ex_flush_en
+    output logic        id_ex_flush_en,
+
+    // -----------------------
+    // Outputs: IF-stage PC redirect controls
+    // -----------------------
+    output logic        pc_redirect_sel,
+    output logic [XLEN-1:0] pc_redirect_target,
+    output logic        pc_redirect_is_trap
 );
 
     // -----------------------
@@ -112,40 +127,63 @@ module hazard_unit
                             ((ex_rd_addr == id_rs1_addr) || (ex_rd_addr == id_rs2_addr));
 
     // -----------------------
+    // PC Redirect Selection (Trap has top priority)
+    // -----------------------
+    always_comb begin
+        pc_redirect_sel      = 1'b0;
+        pc_redirect_target   = '0;
+        pc_redirect_is_trap  = 1'b0;
+
+        if (trap_pc_sel) begin
+            pc_redirect_sel     = 1'b1;
+            pc_redirect_target  = trap_target_pc;
+            pc_redirect_is_trap = 1'b1;
+        end else if (ex_branch_taken) begin
+            pc_redirect_sel     = 1'b1;
+            pc_redirect_target  = ex_branch_target;
+        end
+    end
+
+    // -----------------------
     // Stall and Flush Signal Generation
     // -----------------------
     always_comb begin
         // Defaults: no stalls, no flushes
-        if_stall_en    = 1'b0;
-        if_id_stall_en = 1'b0;
-        id_ex_stall_en = 1'b0;
+        if_stall_en     = 1'b0;
+        if_id_stall_en  = 1'b0;
+        id_ex_stall_en  = 1'b0;
         ex_mem_stall_en = 1'b0;
-        if_id_flush_en = 1'b0;
-        id_ex_flush_en = 1'b0;
-
-        // (1) Memory stall (D-Cache miss): freeze the entire pipeline
-        if (mem_stall_req) begin
-            if_stall_en    = 1'b1;
-            if_id_stall_en = 1'b1;
-            id_ex_stall_en = 1'b1;
-            ex_mem_stall_en = 1'b1;
-        end
+        if_id_flush_en  = 1'b0;
+        id_ex_flush_en  = 1'b0;
 
-        // (2) Load-Use stall: freeze IF and IF/ID, insert bubble into ID/EX
-        if (load_use_stall && !mem_stall_req) begin
-            if_stall_en    = 1'b1;
-            if_id_stall_en = 1'b1;
-            id_ex_flush_en = 1'b1;
-        end
-
-        // (3) Branch/jump misprediction: flush IF/ID and ID/EX
-        // Branch flush overrides load-use stall (the stalled instruction is invalid anyway)
-        if (ex_branch_taken) begin
+        if (trap_flush_req) begin
             if_id_flush_en = 1'b1;
             id_ex_flush_en = 1'b1;
-            // Cancel load-use stall if branch is also taken
-            if_stall_en    = 1'b0;
-            if_id_stall_en = 1'b0;
+        end else begin
+            // (1) Memory stall (D-Cache miss): freeze the entire pipeline
+            if (mem_stall_req) begin
+                if_stall_en     = 1'b1;
+                if_id_stall_en  = 1'b1;
+                id_ex_stall_en  = 1'b1;
+                ex_mem_stall_en = 1'b1;
+            end
+
+            // (2) Load-Use stall: freeze IF and IF/ID, insert bubble into ID/EX
+            if (load_use_stall && !mem_stall_req) begin
+                if_stall_en    = 1'b1;
+                if_id_stall_en = 1'b1;
+                id_ex_flush_en = 1'b1;
+            end
+
+            // (3) Branch/jump misprediction: flush IF/ID and ID/EX
+            // Branch flush overrides load-use stall (the stalled instruction is invalid anyway)
+            if (ex_branch_taken) begin
+                if_id_flush_en = 1'b1;
+                id_ex_flush_en = 1'b1;
+                // Cancel load-use stall if branch is also taken
+                if_stall_en    = 1'b0;
+                if_id_stall_en = 1'b0;
+            end
         end
     end
 
diff --git a/rv64cpu/rtl/core/id_ex_reg.sv b/rv64cpu/rtl/core/id_ex_reg.sv
index e88ce17..9375bb4 100644
--- a/rv64cpu/rtl/core/id_ex_reg.sv
+++ b/rv64cpu/rtl/core/id_ex_reg.sv
@@ -32,6 +32,9 @@ module id_ex_reg
 
     // Inputs from ID Stage
 
+    // Instruction payload
+    input  logic [INST_WIDTH-1:0]  id_instr,
+
     // Data/Operands
     input  logic [XLEN-1:0]        id_pc,
     input  logic [XLEN-1:0]        id_rs1_rdata,
@@ -73,6 +76,9 @@ module id_ex_reg
 
     // Outputs to EX Stage
 
+    // Instruction payload
+    output logic [INST_WIDTH-1:0]  ex_instr,
+
     // Data/Operands
     output logic [XLEN-1:0]        ex_pc,
     output logic [XLEN-1:0]        ex_rs1_rdata,
@@ -114,6 +120,7 @@ module id_ex_reg
 
     always_ff @(posedge clk) begin
         if (rst) begin
+            ex_instr         <= '0;
             ex_pc            <= '0;
             ex_rs1_rdata     <= '0;
             ex_rs2_rdata     <= '0;
@@ -145,6 +152,7 @@ module id_ex_reg
             ex_is_fence      <= '0;
             ex_is_fence_i    <= '0;
         end else if (flush_en) begin
+            ex_instr         <= '0;
             ex_alu_op        <= ALU_ADD; // NOP is effectively ADD x0, x0, 0
             ex_alu_src1_sel  <= '0;
             ex_alu_src2_sel  <= '0;
@@ -170,6 +178,7 @@ module id_ex_reg
             ex_is_fence      <= '0;
             ex_is_fence_i    <= '0;
         end else if (~stall_en) begin
+            ex_instr         <= id_instr;
             ex_pc            <= id_pc;
             ex_rs1_rdata     <= id_rs1_rdata;
             ex_rs2_rdata     <= id_rs2_rdata;
diff --git a/rv64cpu/rtl/core/id_stage.sv b/rv64cpu/rtl/core/id_stage.sv
index 27d3daf..6a8bab9 100644
--- a/rv64cpu/rtl/core/id_stage.sv
+++ b/rv64cpu/rtl/core/id_stage.sv
@@ -26,6 +26,7 @@ module id_stage
     // Inputs from IF Stage (via IF/ID Pipeline Register)
     input  logic [XLEN-1:0]        if_pc,        // PC of the current instruction
     input  logic [INST_WIDTH-1:0]  if_instr,     // The 32-bit instruction fetched
+    input  logic [1:0]             csr_priv_mode, // Current privilege mode from CSR
 
     // Write-back Inputs from WB Stage (to RegFile)
     input  logic                   wb_reg_write_en, // Register write enable from WB stage
@@ -85,6 +86,7 @@ module id_stage
 
     decoder u_decoder (
         .instr          (if_instr),
+        .priv_mode      (csr_priv_mode),
 
         // Outputs to RegFile read ports
         .rs1_addr       (rs1_addr),
diff --git a/rv64cpu/rtl/core/if_stage.sv b/rv64cpu/rtl/core/if_stage.sv
index ebb589c..af6b34a 100644
--- a/rv64cpu/rtl/core/if_stage.sv
+++ b/rv64cpu/rtl/core/if_stage.sv
@@ -23,10 +23,11 @@ module if_stage
     input logic                clk,
     input logic                rst,
 
-    // Pipeline Control Signals (from Hazard Unit & EX Stage)
-    input logic                stall_en,       // Freeze PC (stall), 0: Normal operation
-    input logic                ex_branch_taken,   // Branch taken signal from EX Stage
-    input logic [XLEN-1:0]     ex_branch_target, // Branch target address from EX Stage
+    // Pipeline Control Signals (from Hazard Unit & Trap Controller)
+    input logic                stall_en,          // Freeze PC (stall), 0: Normal operation
+    input logic                pc_redirect_sel,   // Branch/Trap redirect request
+    input logic [XLEN-1:0]     pc_redirect_target,// Redirect target address
+    input logic                pc_redirect_is_trap, // 1: Redirect request comes from trap controller
     
     output logic [XLEN-1:0]    if_pc
 );
@@ -38,19 +39,21 @@ module if_stage
     logic [XLEN-1:0] next_pc;
 
     always_comb begin
-        if (ex_branch_taken) begin
-            next_pc = ex_branch_target;
-        end else begin
-            next_pc = pc_reg + 64'd4;
-        end
+        next_pc = pc_reg + 64'd4;
     end
 
     // Sequential Logic: Update PC Register
     always_ff @(posedge clk) begin
         if (rst) begin
             pc_reg <= 64'h0000_0000_8000_0000;
+        end else if (pc_redirect_sel && pc_redirect_is_trap) begin
+            pc_reg <= pc_redirect_target;
         end else if (~stall_en) begin
-            pc_reg <= next_pc;
+            if (pc_redirect_sel) begin
+                pc_reg <= pc_redirect_target;
+            end else begin
+                pc_reg <= next_pc;
+            end
         end
     end
     
diff --git a/rv64cpu/rtl/core/mem_stage.sv b/rv64cpu/rtl/core/mem_stage.sv
index a63a456..558d6d6 100644
--- a/rv64cpu/rtl/core/mem_stage.sv
+++ b/rv64cpu/rtl/core/mem_stage.sv
@@ -31,6 +31,7 @@ module mem_stage
     input  logic [4:0]             mem_rs1_addr,
     input  logic [XLEN-1:0]        mem_pc,
     input  logic [XLEN-1:0]        mem_imm,
+    input  logic [INST_WIDTH-1:0]  mem_instr,
 
     // Memory Control
     input  logic                   mem_is_load,
@@ -69,6 +70,7 @@ module mem_stage
     output logic [XLEN-1:0]        mem_wb_alu_result,
     output logic [XLEN-1:0]        mem_wb_mem_rdata,
     output logic [XLEN-1:0]        mem_wb_pc,
+    output logic [INST_WIDTH-1:0]  mem_wb_instr,
 
     output logic                   mem_wb_reg_write_en,
     output logic [4:0]             mem_wb_rd_addr,
@@ -85,6 +87,9 @@ module mem_stage
     output logic                   mem_wb_is_ebreak,
     output logic                   mem_wb_is_mret,
     output logic                   mem_wb_is_sret,
+    output logic                   mem_wb_load_fault,
+    output logic                   mem_wb_store_fault,
+    output logic [XLEN-1:0]        mem_wb_fault_addr,
 
     // Control to Hazard Unit / Stall Logic
     output logic                   mem_stall_req      // Stall pipeline if D-Cache doesn't respond
@@ -93,11 +98,31 @@ module mem_stage
     logic [XLEN-1:0] load_data_aligned;
     logic [XLEN-1:0] store_data_aligned;
     logic [7:0]      write_strobe;
+    logic            load_addr_misaligned;
+    logic            store_addr_misaligned;
+
+    function automatic logic addr_misaligned(
+        input logic [2:0]      size,
+        input logic [XLEN-1:0] addr
+    );
+        logic result;
+        case (size)
+            3'b000, 3'b100: result = 1'b0;         // Byte L/S
+            3'b001, 3'b101: result = addr[0];      // Halfword requires bit0 = 0
+            3'b010, 3'b110: result = |addr[1:0];   // Word requires bits[1:0] = 0
+            3'b011:          result = |addr[2:0];   // Doubleword requires bits[2:0] = 0
+            default:         result = 1'b0;
+        endcase
+        return result;
+    endfunction
+
+    assign load_addr_misaligned  = mem_is_load  && addr_misaligned(mem_mem_size, mem_alu_result);
+    assign store_addr_misaligned = mem_is_store && addr_misaligned(mem_mem_size, mem_alu_result);
 
     // --------------------------
     // Memory Request Logic
-    assign dmem_read_req  = mem_is_load;
-    assign dmem_write_req = mem_is_store;
+    assign dmem_read_req  = mem_is_load  & ~load_addr_misaligned;
+    assign dmem_write_req = mem_is_store & ~store_addr_misaligned;
     assign dmem_addr      = mem_alu_result; // ALU result is the computed address
 
     // --------------------------
@@ -194,6 +219,7 @@ module mem_stage
     assign mem_wb_alu_result    = mem_alu_result;
     assign mem_wb_mem_rdata     = load_data_aligned;
     assign mem_wb_pc            = mem_pc;
+    assign mem_wb_instr         = mem_instr;
 
     assign mem_wb_reg_write_en  = mem_reg_write_en;
     assign mem_wb_rd_addr       = mem_rd_addr;
@@ -210,5 +236,8 @@ module mem_stage
     assign mem_wb_is_ebreak     = mem_is_ebreak;
     assign mem_wb_is_mret       = mem_is_mret;
     assign mem_wb_is_sret       = mem_is_sret;
+    assign mem_wb_load_fault    = load_addr_misaligned;
+    assign mem_wb_store_fault   = store_addr_misaligned;
+    assign mem_wb_fault_addr    = (load_addr_misaligned | store_addr_misaligned) ? mem_alu_result : '0;
 
 endmodule
diff --git a/rv64cpu/rtl/core/mem_wb_reg.sv b/rv64cpu/rtl/core/mem_wb_reg.sv
index a70057c..6e8e13f 100644
--- a/rv64cpu/rtl/core/mem_wb_reg.sv
+++ b/rv64cpu/rtl/core/mem_wb_reg.sv
@@ -36,6 +36,7 @@ module mem_wb_reg
     input  logic [XLEN-1:0]        mem_pc,
     input  logic [XLEN-1:0]        mem_alu_result,
     input  logic [XLEN-1:0]        mem_mem_rdata,
+    input  logic [INST_WIDTH-1:0]  mem_instr,
 
     // Write back control
     input  logic                   mem_reg_write_en,
@@ -53,6 +54,9 @@ module mem_wb_reg
     input  logic                   mem_is_ebreak,
     input  logic                   mem_is_mret,
     input  logic                   mem_is_sret,
+    input  logic                   mem_load_fault,
+    input  logic                   mem_store_fault,
+    input  logic [XLEN-1:0]        mem_fault_addr,
 
     // -----------------------
     // Outputs to WB Stage
@@ -61,6 +65,7 @@ module mem_wb_reg
     output logic [XLEN-1:0]        wb_pc,
     output logic [XLEN-1:0]        wb_alu_result,
     output logic [XLEN-1:0]        wb_mem_rdata,
+    output logic [INST_WIDTH-1:0]  wb_instr,
 
     // Write back control
     output logic                   wb_reg_write_en,
@@ -77,7 +82,10 @@ module mem_wb_reg
     output logic                   wb_is_ecall,
     output logic                   wb_is_ebreak,
     output logic                   wb_is_mret,
-    output logic                   wb_is_sret
+    output logic                   wb_is_sret,
+    output logic                   wb_load_fault,
+    output logic                   wb_store_fault,
+    output logic [XLEN-1:0]        wb_fault_addr
 
 );
     // Sequential Logic: State Update
@@ -86,6 +94,7 @@ module mem_wb_reg
             wb_pc            <= '0;
             wb_alu_result    <= '0;
             wb_mem_rdata     <= '0;
+            wb_instr         <= '0;
             wb_reg_write_en  <= '0;
             wb_rd_addr       <= '0;
             wb_wb_sel        <= '0;
@@ -99,6 +108,9 @@ module mem_wb_reg
             wb_is_ebreak     <= '0;
             wb_is_mret       <= '0;
             wb_is_sret       <= '0;
+            wb_load_fault    <= '0;
+            wb_store_fault   <= '0;
+            wb_fault_addr    <= '0;
         end else if (flush_en) begin
             // Target specific control signals to clear. Leave datapath elements intact
             // to avoid extreme power consumption from massive flip-flop state changes array.
@@ -109,10 +121,14 @@ module mem_wb_reg
             wb_is_ebreak     <= '0;
             wb_is_mret       <= '0;
             wb_is_sret       <= '0;
+            wb_load_fault    <= '0;
+            wb_store_fault   <= '0;
+            wb_fault_addr    <= '0;
         end else if (!stall_en) begin
             wb_pc            <= mem_pc;
             wb_alu_result    <= mem_alu_result;
             wb_mem_rdata     <= mem_mem_rdata;
+            wb_instr         <= mem_instr;
             wb_reg_write_en  <= mem_reg_write_en;
             wb_rd_addr       <= mem_rd_addr;
             wb_wb_sel        <= mem_wb_sel;
@@ -126,6 +142,9 @@ module mem_wb_reg
             wb_is_ebreak     <= mem_is_ebreak;
             wb_is_mret       <= mem_is_mret;
             wb_is_sret       <= mem_is_sret;
+            wb_load_fault    <= mem_load_fault;
+            wb_store_fault   <= mem_store_fault;
+            wb_fault_addr    <= mem_fault_addr;
         end
     end
 
diff --git a/rv64cpu/rtl/core/richard_core.sv b/rv64cpu/rtl/core/richard_core.sv
index ae73e77..ad75cc8 100644
--- a/rv64cpu/rtl/core/richard_core.sv
+++ b/rv64cpu/rtl/core/richard_core.sv
@@ -34,8 +34,15 @@ module richard_core
     output logic [63:0] dmem_addr,
     output logic [63:0] dmem_wdata,
     output logic [2:0]  dmem_size,
-    input  logic [63:0] dmem_rdata
+    input  logic [63:0] dmem_rdata,
+
+    // Interface 3: External Interrupt Sources
+    input  logic        ext_timer_int,
+    input  logic        ext_software_int,
+    input  logic        ext_external_int
 );
+    localparam int CSR_MSTATUS_MIE_BIT = 3;
+
     // -----------------------
     // Internal Wire Declarations
     // -----------------------
@@ -44,6 +51,8 @@ module richard_core
     logic [1:0]        hu_forward_a_sel, hu_forward_b_sel;
     logic              hu_if_stall_en, hu_if_id_stall_en, hu_id_ex_stall_en, hu_ex_mem_stall_en;
     logic              hu_if_id_flush_en, hu_id_ex_flush_en;
+    logic              hu_pc_redirect_sel, hu_pc_redirect_is_trap;
+    logic [XLEN-1:0]   hu_pc_redirect_target;
 
     // (2) IF Stage Outputs
     logic [XLEN-1:0]   if_pc_out;
@@ -74,6 +83,7 @@ module richard_core
 
     // (5) ID/EX Pipeline Register Outputs
     logic [XLEN-1:0]   ex_pc_in;
+    logic [INST_WIDTH-1:0] ex_instr_in;
     logic [XLEN-1:0]   ex_rs1_rdata_in, ex_rs2_rdata_in;
     logic [4:0]        ex_rs1_addr_in, ex_rs2_addr_in;
     logic [XLEN-1:0]   ex_imm_in;
@@ -99,6 +109,7 @@ module richard_core
 
     // (7) EX/MEM Pipeline Register Outputs
     logic [XLEN-1:0]   mem_pc_in;
+    logic [INST_WIDTH-1:0] mem_instr_in;
     logic [XLEN-1:0]   mem_alu_result_in;
     logic              mem_branch_taken_in;
     logic [XLEN-1:0]   mem_branch_target_in;
@@ -119,6 +130,7 @@ module richard_core
     logic [XLEN-1:0]   mw_reg_alu_result_in;
     logic [XLEN-1:0]   mw_reg_mem_rdata_in;
     logic [XLEN-1:0]   mw_reg_pc_in;
+    logic [INST_WIDTH-1:0] mw_reg_instr_in;
     logic [7:0]        mw_reg_dmem_wstrb_in;
     logic              mw_reg_reg_write_en_in;
     logic [4:0]        mw_reg_rd_addr_in;
@@ -129,12 +141,15 @@ module richard_core
     logic [4:0]        mw_reg_rs1_addr_in;
     logic [XLEN-1:0]   mw_reg_imm_in;
     logic              mw_reg_illegal_instr_in, mw_reg_is_ecall_in, mw_reg_is_ebreak_in, mw_reg_is_mret_in, mw_reg_is_sret_in;
+    logic              mw_reg_load_fault_in, mw_reg_store_fault_in;
+    logic [XLEN-1:0]   mw_reg_fault_addr_in;
     logic              mem_stall_req;
 
     // (9) MEM/WB Pipeline Register Outputs
     logic [XLEN-1:0]   wb_pc_in;
     logic [XLEN-1:0]   wb_alu_result_in;
     logic [XLEN-1:0]   wb_mem_rdata_in;
+    logic [INST_WIDTH-1:0] wb_instr_in;
     logic              wb_reg_write_en_in;
     logic [4:0]        wb_rd_addr_in;
     logic [1:0]        wb_wb_sel_in;
@@ -144,6 +159,8 @@ module richard_core
     logic [4:0]        wb_rs1_addr_in;
     logic [XLEN-1:0]   wb_imm_in;
     logic              wb_illegal_instr_in, wb_is_ecall_in, wb_is_ebreak_in, wb_is_mret_in, wb_is_sret_in;
+    logic              wb_load_fault_flag, wb_store_fault_flag;
+    logic [XLEN-1:0]   wb_fault_addr_in;
 
     // (10) WB Stage Outputs (to RegFile & CSR Unit)
     logic [XLEN-1:0]   wb_rd_wdata;
@@ -172,6 +189,32 @@ module richard_core
     logic              trap_illegal_instr, trap_is_ecall, trap_is_ebreak, trap_is_mret, trap_is_sret;
     logic [XLEN-1:0]   trap_epc;
 
+    // (12) Trap Controller + interrupt wiring
+    logic              trap_load_fault, trap_store_fault;
+    logic              trap_instr_page_fault, trap_load_page_fault, trap_store_page_fault;
+    logic [XLEN-1:0]   trap_bad_addr;
+    logic [INST_WIDTH-1:0] trap_bad_instr;
+    logic              trap_flush_req;
+    logic              trap_pc_sel;
+    logic [XLEN-1:0]   trap_next_pc;
+    logic              trap_pc_sel_raw;
+    logic [XLEN-1:0]   trap_next_pc_raw;
+    logic              trap_ctrl_trigger;
+    logic [XLEN-1:0]   trap_ctrl_mepc;
+    logic [XLEN-1:0]   trap_ctrl_mcause;
+    logic [XLEN-1:0]   trap_ctrl_mtval;
+    logic              trap_ctrl_to_s_mode_flag;
+    logic              trap_ctrl_mret_en;
+    logic              trap_ctrl_sret_en;
+    logic              csr_mstatus_mie;
+
+    // Page-fault paths remain stubbed until the MMU surfaces violations.
+    assign trap_instr_page_fault  = 1'b0;
+    assign trap_load_page_fault   = 1'b0;
+    assign trap_store_page_fault  = 1'b0;
+
+    assign csr_mstatus_mie        = csr_mstatus_value[CSR_MSTATUS_MIE_BIT];
+
     // ---------------------------------------------------------
     // (A) Hazard Unit Implementation
     // ---------------------------------------------------------
@@ -184,9 +227,13 @@ module richard_core
         .ex_reg_write_en    (ex_reg_write_en_in),
         .ex_is_load         (ex_is_load_in),
         .ex_branch_taken    (ex_branch_taken_out),
+        .ex_branch_target   (ex_branch_target_out),
         .mem_rd_addr        (mem_rd_addr_in),
         .mem_reg_write_en   (mem_reg_write_en_in),
         .mem_stall_req      (mem_stall_req),
+        .trap_flush_req     (trap_flush_req),
+        .trap_pc_sel        (trap_pc_sel),
+        .trap_target_pc     (trap_next_pc),
         .wb_rd_addr         (wb_rd_addr_in),
         .wb_reg_write_en    (wb_reg_write_en_out),
         .forward_a_sel      (hu_forward_a_sel),
@@ -196,7 +243,10 @@ module richard_core
         .id_ex_stall_en     (hu_id_ex_stall_en),
         .ex_mem_stall_en    (hu_ex_mem_stall_en),
         .if_id_flush_en     (hu_if_id_flush_en),
-        .id_ex_flush_en     (hu_id_ex_flush_en)
+        .id_ex_flush_en     (hu_id_ex_flush_en),
+        .pc_redirect_sel    (hu_pc_redirect_sel),
+        .pc_redirect_target (hu_pc_redirect_target),
+        .pc_redirect_is_trap(hu_pc_redirect_is_trap)
     );
 
     // ---------------------------------------------------------
@@ -206,8 +256,9 @@ module richard_core
         .clk                (clk),
         .rst                (rst),
         .stall_en           (hu_if_stall_en),
-        .ex_branch_taken    (ex_branch_taken_out),
-        .ex_branch_target   (ex_branch_target_out),
+        .pc_redirect_sel    (hu_pc_redirect_sel),
+        .pc_redirect_target (hu_pc_redirect_target),
+        .pc_redirect_is_trap(hu_pc_redirect_is_trap),
         .if_pc              (if_pc_out)
     );
 
@@ -232,6 +283,7 @@ module richard_core
         .rst                (rst),
         .if_pc              (if_id_pc),
         .if_instr           (if_id_instr),
+        .csr_priv_mode      (csr_priv_mode_cur),
         .wb_reg_write_en    (wb_reg_write_en_out),
         .wb_rd_addr         (wb_rd_addr),
         .wb_rd_wdata        (wb_rd_wdata),
@@ -272,6 +324,7 @@ module richard_core
         .rst                (rst),
         .stall_en           (hu_id_ex_stall_en),
         .flush_en           (hu_id_ex_flush_en),
+        .id_instr           (if_id_instr),
         .id_pc              (id_pc_out),
         .id_rs1_rdata       (id_rs1_rdata),
         .id_rs2_rdata       (id_rs2_rdata),
@@ -303,6 +356,7 @@ module richard_core
         .id_is_fence        (id_is_fence),
         .id_is_fence_i      (id_is_fence_i),
         .ex_pc              (ex_pc_in),
+        .ex_instr           (ex_instr_in),
         .ex_rs1_rdata       (ex_rs1_rdata_in),
         .ex_rs2_rdata       (ex_rs2_rdata_in),
         .ex_rs1_addr        (ex_rs1_addr_in),
@@ -386,6 +440,7 @@ module richard_core
         .ex_rs1_addr        (ex_rs1_addr_in),
         .ex_pc              (ex_pc_in),
         .ex_imm             (ex_imm_in),
+        .ex_instr           (ex_instr_in),
         .ex_is_load         (ex_is_load_in),
         .ex_is_store        (ex_is_store_in),
         .ex_mem_size        (ex_mem_size_in),
@@ -411,6 +466,7 @@ module richard_core
         .mem_rs1_addr        (mem_rs1_addr_in),
         .mem_pc              (mem_pc_in),
         .mem_imm             (mem_imm_in),
+        .mem_instr           (mem_instr_in),
         .mem_is_load         (mem_is_load_in),
         .mem_is_store        (mem_is_store_in),
         .mem_mem_size        (mem_mem_size_in),
@@ -442,6 +498,7 @@ module richard_core
         .mem_rs1_addr        (mem_rs1_addr_in),
         .mem_pc              (mem_pc_in),
         .mem_imm             (mem_imm_in),
+        .mem_instr           (mem_instr_in),
         .mem_is_load         (mem_is_load_in),
         .mem_is_store        (mem_is_store_in),
         .mem_mem_size        (mem_mem_size_in),
@@ -470,6 +527,7 @@ module richard_core
         .mem_wb_alu_result   (mw_reg_alu_result_in),
         .mem_wb_mem_rdata    (mw_reg_mem_rdata_in),
         .mem_wb_pc           (mw_reg_pc_in),
+        .mem_wb_instr        (mw_reg_instr_in),
         .mem_wb_reg_write_en (mw_reg_reg_write_en_in),
         .mem_wb_rd_addr      (mw_reg_rd_addr_in),
         .mem_wb_wb_sel       (mw_reg_wb_sel_in),
@@ -483,19 +541,23 @@ module richard_core
         .mem_wb_is_ebreak    (mw_reg_is_ebreak_in),
         .mem_wb_is_mret      (mw_reg_is_mret_in),
         .mem_wb_is_sret      (mw_reg_is_sret_in),
+        .mem_wb_load_fault   (mw_reg_load_fault_in),
+        .mem_wb_store_fault  (mw_reg_store_fault_in),
+        .mem_wb_fault_addr   (mw_reg_fault_addr_in),
         .mem_stall_req       (mem_stall_req)
     );
 
     assign dmem_size = mem_mem_size_in;
 
     mem_wb_reg u_mem_wb_reg (
-        .clk                (clk),
-        .rst                (rst),
-        .stall_en           (1'b0),
-        .flush_en           (1'b0),
+        .clk                 (clk),
+        .rst                 (rst),
+        .stall_en            (1'b0),
+        .flush_en            (trap_flush_req),
         .mem_pc              (mw_reg_pc_in),
         .mem_alu_result      (mw_reg_alu_result_in),
         .mem_mem_rdata       (mw_reg_mem_rdata_in),
+        .mem_instr           (mw_reg_instr_in),
         .mem_reg_write_en    (mw_reg_reg_write_en_in),
         .mem_rd_addr         (mw_reg_rd_addr_in),
         .mem_wb_sel          (mw_reg_wb_sel_in),
@@ -509,9 +571,13 @@ module richard_core
         .mem_is_ebreak       (mw_reg_is_ebreak_in),
         .mem_is_mret         (mw_reg_is_mret_in),
         .mem_is_sret         (mw_reg_is_sret_in),
+        .mem_load_fault      (mw_reg_load_fault_in),
+        .mem_store_fault     (mw_reg_store_fault_in),
+        .mem_fault_addr      (mw_reg_fault_addr_in),
         .wb_pc               (wb_pc_in),
         .wb_alu_result       (wb_alu_result_in),
         .wb_mem_rdata        (wb_mem_rdata_in),
+        .wb_instr            (wb_instr_in),
         .wb_reg_write_en     (wb_reg_write_en_in),
         .wb_rd_addr          (wb_rd_addr_in),
         .wb_wb_sel           (wb_wb_sel_in),
@@ -524,7 +590,10 @@ module richard_core
         .wb_is_ecall         (wb_is_ecall_in),
         .wb_is_ebreak        (wb_is_ebreak_in),
         .wb_is_mret          (wb_is_mret_in),
-        .wb_is_sret          (wb_is_sret_in)
+        .wb_is_sret          (wb_is_sret_in),
+        .wb_load_fault       (wb_load_fault_flag),
+        .wb_store_fault      (wb_store_fault_flag),
+        .wb_fault_addr       (wb_fault_addr_in)
     );
 
     // ---------------------------------------------------------
@@ -543,12 +612,17 @@ module richard_core
         .mem_wb_rs1_rdata   (wb_rs1_rdata_in),
         .mem_wb_rs1_addr    (wb_rs1_addr_in),
         .mem_wb_imm         (wb_imm_in),
+        .mem_wb_instr       (wb_instr_in),
         .mem_wb_illegal_instr(wb_illegal_instr_in),
         .mem_wb_is_ecall    (wb_is_ecall_in),
         .mem_wb_is_ebreak   (wb_is_ebreak_in),
         .mem_wb_is_mret     (wb_is_mret_in),
         .mem_wb_is_sret     (wb_is_sret_in),
+        .mem_wb_load_fault  (wb_load_fault_flag),
+        .mem_wb_store_fault (wb_store_fault_flag),
+        .mem_wb_fault_addr  (wb_fault_addr_in),
         .csr_rdata          (csr_rdata),
+        .csr_illegal_access (csr_illegal_access_flag),
         .wb_rd_wdata        (wb_rd_wdata),
         .wb_rd_addr         (wb_rd_addr),
         .wb_reg_write_en    (wb_reg_write_en_out),
@@ -561,7 +635,11 @@ module richard_core
         .trap_is_ebreak     (trap_is_ebreak),
         .trap_is_mret       (trap_is_mret),
         .trap_is_sret       (trap_is_sret),
-        .trap_epc           (trap_epc)
+        .trap_epc           (trap_epc),
+        .trap_load_fault    (trap_load_fault),
+        .trap_store_fault   (trap_store_fault),
+        .trap_bad_addr      (trap_bad_addr),
+        .trap_bad_instr     (trap_bad_instr)
     );
 
     csr_unit u_csr_unit (
@@ -571,12 +649,13 @@ module richard_core
         .csr_op             (csr_op),
         .csr_addr           (csr_addr),
         .csr_rs1_data       (csr_rs1_data),
-        .trap_illegal_instr (trap_illegal_instr),
-        .trap_is_ecall      (trap_is_ecall),
-        .trap_is_ebreak     (trap_is_ebreak),
-        .trap_is_mret       (trap_is_mret),
-        .trap_is_sret       (trap_is_sret),
-        .trap_epc           (trap_epc),
+        .trap_ctrl_trigger  (trap_ctrl_trigger),
+        .trap_ctrl_to_s_mode(trap_ctrl_to_s_mode_flag),
+        .trap_ctrl_mepc     (trap_ctrl_mepc),
+        .trap_ctrl_mcause   (trap_ctrl_mcause),
+        .trap_ctrl_mtval    (trap_ctrl_mtval),
+        .trap_ctrl_mret_en  (trap_ctrl_mret_en),
+        .trap_ctrl_sret_en  (trap_ctrl_sret_en),
         .csr_rdata          (csr_rdata),
         .csr_mstatus        (csr_mstatus_value),
         .csr_sstatus        (csr_sstatus_value),
@@ -587,10 +666,52 @@ module richard_core
         .csr_mepc           (csr_mepc_value),
         .csr_sepc           (csr_sepc_value),
         .csr_satp           (csr_satp_value),
-        .csr_priv_mode      (csr_priv_mode_cur),
-        .csr_trap_vector    (csr_trap_vector_value),
-        .csr_trap_to_s_mode (csr_trap_to_s_mode_flag),
-        .csr_illegal_access (csr_illegal_access_flag)
+        .csr_priv_mode          (csr_priv_mode_cur),
+        .csr_trap_vector        (),
+        .csr_trap_to_s_mode     (),
+        .csr_trap_vector_next   (csr_trap_vector_value),
+        .csr_trap_to_s_mode_next(csr_trap_to_s_mode_flag),
+        .csr_illegal_access     (csr_illegal_access_flag)
     );
 
+    trap_ctrl u_trap_ctrl (
+        .wb_pc               (wb_pc_in),
+        .trap_illegal_instr  (trap_illegal_instr),
+        .trap_is_ecall       (trap_is_ecall),
+        .trap_is_ebreak      (trap_is_ebreak),
+        .trap_is_mret        (trap_is_mret),
+        .trap_is_sret        (trap_is_sret),
+        .trap_load_fault     (trap_load_fault),
+        .trap_store_fault    (trap_store_fault),
+        .trap_instr_page_fault(trap_instr_page_fault),
+        .trap_load_page_fault(trap_load_page_fault),
+        .trap_store_page_fault(trap_store_page_fault),
+        .trap_bad_addr       (trap_bad_addr),
+        .trap_bad_instr      (trap_bad_instr),
+        .ext_timer_int       (ext_timer_int),
+        .ext_software_int    (ext_software_int),
+        .ext_external_int    (ext_external_int),
+        .csr_mstatus_mie     (csr_mstatus_mie),
+        .csr_mtvec           (csr_mtvec_base),
+        .csr_stvec           (csr_stvec_base),
+        .csr_mepc            (csr_mepc_value),
+        .csr_sepc            (csr_sepc_value),
+        .csr_medeleg         (csr_medeleg_value),
+        .csr_mideleg         (csr_mideleg_value),
+        .csr_priv_mode       (csr_priv_mode_cur),
+        .trap_trigger        (trap_ctrl_trigger),
+        .trap_mepc           (trap_ctrl_mepc),
+        .trap_mcause         (trap_ctrl_mcause),
+        .trap_mtval          (trap_ctrl_mtval),
+        .trap_to_s_mode      (trap_ctrl_to_s_mode_flag),
+        .mret_en             (trap_ctrl_mret_en),
+        .sret_en             (trap_ctrl_sret_en),
+        .trap_flush_req      (trap_flush_req),
+        .trap_pc_sel         (trap_pc_sel_raw),
+        .trap_next_pc        (trap_next_pc_raw)
+    );
+
+    assign trap_pc_sel = trap_pc_sel_raw;
+    assign trap_next_pc = trap_next_pc_raw;
+
 endmodule
diff --git a/rv64cpu/rtl/core/wb_stage.sv b/rv64cpu/rtl/core/wb_stage.sv
index 26c9c7b..d9bfd93 100644
--- a/rv64cpu/rtl/core/wb_stage.sv
+++ b/rv64cpu/rtl/core/wb_stage.sv
@@ -26,6 +26,7 @@ module wb_stage
     input  logic [XLEN-1:0]        mem_wb_mem_rdata,
     input  logic [XLEN-1:0]        mem_wb_pc,
     input  logic [XLEN-1:0]        mem_wb_pc_plus_4,
+    input  logic [INST_WIDTH-1:0]  mem_wb_instr,
     
     input  logic                   mem_wb_reg_write_en,
     input  logic [4:0]             mem_wb_rd_addr,
@@ -42,9 +43,13 @@ module wb_stage
     input  logic                   mem_wb_is_ebreak,
     input  logic                   mem_wb_is_mret,
     input  logic                   mem_wb_is_sret,
+    input  logic                   mem_wb_load_fault,
+    input  logic                   mem_wb_store_fault,
+    input  logic [XLEN-1:0]        mem_wb_fault_addr,
 
     // Inputs from CSR Unit
     input  logic [XLEN-1:0]        csr_rdata,         // Data read from CSR unit
+    input  logic                   csr_illegal_access,// CSR rejected the request
 
     // Outputs to Register File
     output logic [XLEN-1:0]        wb_rd_wdata,
@@ -63,14 +68,21 @@ module wb_stage
     output logic                   trap_is_ebreak,
     output logic                   trap_is_mret,
     output logic                   trap_is_sret,
-    output logic [XLEN-1:0]        trap_epc           // PC of the instruction causing the trap
+    output logic [XLEN-1:0]        trap_epc,
+    output logic                   trap_load_fault,
+    output logic                   trap_store_fault,
+    output logic [XLEN-1:0]        trap_bad_addr,
+    output logic [INST_WIDTH-1:0]  trap_bad_instr
 );
 
     // --------------------------
     // Exception/Trap Detection
     // --------------------------
     logic has_trap;
-    assign has_trap = mem_wb_illegal_instr | mem_wb_is_ecall | mem_wb_is_ebreak;
+    logic trap_blocker;
+    assign has_trap     = mem_wb_illegal_instr | mem_wb_is_ecall | mem_wb_is_ebreak |
+                          mem_wb_load_fault | mem_wb_store_fault;
+    assign trap_blocker = has_trap | csr_illegal_access;
 
     // --------------------------
     // CSR Signal Routing
@@ -106,16 +118,20 @@ module wb_stage
     // --------------------------
     // We only write back if the instruction didn't trap.
     assign wb_rd_addr      = mem_wb_rd_addr;
-    assign wb_reg_write_en = mem_wb_reg_write_en & ~has_trap;
+    assign wb_reg_write_en = mem_wb_reg_write_en & ~trap_blocker;
 
     // --------------------------
     // Trap / Exception Signals
     // --------------------------
-    assign trap_illegal_instr = mem_wb_illegal_instr;
+    assign trap_illegal_instr = mem_wb_illegal_instr | csr_illegal_access;
     assign trap_is_ecall      = mem_wb_is_ecall;
     assign trap_is_ebreak     = mem_wb_is_ebreak;
     assign trap_is_mret       = mem_wb_is_mret;
     assign trap_is_sret       = mem_wb_is_sret;
     assign trap_epc           = mem_wb_pc;
+    assign trap_load_fault    = mem_wb_load_fault;
+    assign trap_store_fault   = mem_wb_store_fault;
+    assign trap_bad_addr      = mem_wb_fault_addr;
+    assign trap_bad_instr     = mem_wb_instr;
 
 endmodule