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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 02:59:33 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 02:59:33 +0800 |
| commit | bc3ec25107314be3cd816c0b669d82338e892806 (patch) | |
| tree | ff3e69ce6be1218be8bd0dd04e0c75760776d7dc /rv64cpu/tb/CMakeLists.txt | |
| parent | c67ba709482821f37d63601b001ac07e6db867b6 (diff) | |
| download | rcc-project-bc3ec25107314be3cd816c0b669d82338e892806.tar.gz rcc-project-bc3ec25107314be3cd816c0b669d82338e892806.tar.xz | |
checkpoint: preserve current RV64 CPU development state
Diffstat (limited to 'rv64cpu/tb/CMakeLists.txt')
| -rw-r--r-- | rv64cpu/tb/CMakeLists.txt | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt index 1312860..33a6224 100644 --- a/rv64cpu/tb/CMakeLists.txt +++ b/rv64cpu/tb/CMakeLists.txt @@ -81,6 +81,7 @@ add_verilator_target( SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv ${RTL_CORE_DIR}/decoder.sv ${RTL_CORE_DIR}/regfile.sv + ${RTL_CORE_DIR}/fp_regfile.sv ${RTL_CORE_DIR}/id_stage.sv INCLUDE_DIRS ${RTL_COMMON_INCLUDES} TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_id_stage.cc @@ -189,6 +190,27 @@ add_verilator_target( TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_tlb.cc ) +add_verilator_target( + NAME tb_ptw + TOP_MODULE ptw + SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv + ${RTL_CORE_DIR}/mmu/ptw.sv + INCLUDE_DIRS ${RTL_COMMON_INCLUDES} + TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_ptw.cc +) + +add_verilator_target( + NAME tb_mmu_top + TOP_MODULE mmu_top + SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv + ${RTL_CORE_DIR}/mmu/tlb.sv + ${RTL_CORE_DIR}/mmu/ptw.sv + ${RTL_CORE_DIR}/mmu/mmu_top.sv + INCLUDE_DIRS ${RTL_COMMON_INCLUDES} + TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_mmu_top.cc + EXTRA_FLAGS -Wno-VARHIDDEN +) + # ═══════════════════════════════════════════════════════════════════════════════════ # Core Integration Test # ═══════════════════════════════════════════════════════════════════════════════════ @@ -199,13 +221,16 @@ add_verilator_target( SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv ${RTL_CORE_DIR}/alu.sv ${RTL_CORE_DIR}/branch_unit.sv + ${RTL_CORE_DIR}/compressed_decoder.sv ${RTL_CORE_DIR}/decoder.sv ${RTL_CORE_DIR}/regfile.sv + ${RTL_CORE_DIR}/fp_regfile.sv ${RTL_CORE_DIR}/if_stage.sv ${RTL_CORE_DIR}/if_id_reg.sv ${RTL_CORE_DIR}/id_stage.sv ${RTL_CORE_DIR}/id_ex_reg.sv ${RTL_CORE_DIR}/ex_stage.sv + ${RTL_CORE_DIR}/fpu/fpu_unit.sv ${RTL_CORE_DIR}/ex_mem_reg.sv ${RTL_CORE_DIR}/mem_stage.sv ${RTL_CORE_DIR}/mem_wb_reg.sv @@ -213,6 +238,10 @@ add_verilator_target( ${RTL_CORE_DIR}/hazard_unit.sv ${RTL_CORE_DIR}/include/csr_pkg.sv ${RTL_CORE_DIR}/csr_unit.sv + ${RTL_CORE_DIR}/pmp_checker.sv + ${RTL_CORE_DIR}/mmu/tlb.sv + ${RTL_CORE_DIR}/mmu/ptw.sv + ${RTL_CORE_DIR}/mmu/mmu_top.sv ${RTL_CORE_DIR}/trap_ctrl.sv ${RTL_CORE_DIR}/richard_core.sv INCLUDE_DIRS ${RTL_COMMON_INCLUDES} |