ID/EX Pipeline Register and tests

3 files changed, 354 insertions, 0 deletions

diff --git a/rv64cpu/rtl/core/id_ex_reg.sv b/rv64cpu/rtl/core/id_ex_reg.sv
new file mode 100644
index 0000000..b8a3bd7
--- /dev/null
+++ b/rv64cpu/rtl/core/id_ex_reg.sv
@@ -0,0 +1,174 @@
+//     Richard CPU
+//     Copyright (C) 2026  Richard Qin
+
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+// File path: rtl/core/id_ex_reg.sv
+// Description: ID/EX Pipeline Register
+//              Latches control signals and data from ID stage and passes them to EX stage.
+//              Supports stall (freeze) and flush.
+
+module id_ex_reg
+    import rv64_pkg::*;
+(
+    input  logic                   clk,
+    input  logic                   rst,
+
+    // Pipeline Control
+    input  logic                   stall_en,
+    input  logic                   flush_en,
+
+
+    // Inputs from ID Stage
+
+    // Data/Operands
+    input  logic [XLEN-1:0]        id_pc,
+    input  logic [XLEN-1:0]        id_rs1_rdata,
+    input  logic [XLEN-1:0]        id_rs2_rdata,
+    input  logic [XLEN-1:0]        id_imm,
+
+    // Execution Control
+    input  alu_op_t                id_alu_op,
+    input  logic                   id_alu_src1_sel,
+    input  logic                   id_alu_src2_sel,
+    input  logic                   id_is_word_op,
+    input  logic                   id_is_branch,
+    input  branch_op_t             id_branch_op,
+    input  logic                   id_is_jump,
+
+    // Memory & Writeback Control
+    input  logic                   id_is_load,
+    input  logic                   id_is_store,
+    input  logic [2:0]             id_mem_size,
+    input  logic                   id_reg_write_en,
+    input  logic [4:0]             id_rd_addr,
+    input  logic [1:0]             id_wb_sel,
+
+    // System / Exception
+    input  logic                   id_is_csr,
+    input  logic [2:0]             id_csr_op,
+    input  logic                   id_illegal_instr,
+    input  logic                   id_is_ecall,
+    input  logic                   id_is_ebreak,
+    input  logic                   id_is_mret,
+    input  logic                   id_is_sret,
+    input  logic                   id_is_wfi,
+    input  logic                   id_is_sfence_vma,
+    input  logic                   id_is_fence,
+    input  logic                   id_is_fence_i,
+
+
+    // Outputs to EX Stage
+
+    // Data/Operands
+    output logic [XLEN-1:0]        ex_pc,
+    output logic [XLEN-1:0]        ex_rs1_rdata,
+    output logic [XLEN-1:0]        ex_rs2_rdata,
+    output logic [XLEN-1:0]        ex_imm,
+
+    // Execution Control
+    output alu_op_t                ex_alu_op,
+    output logic                   ex_alu_src1_sel,
+    output logic                   ex_alu_src2_sel,
+    output logic                   ex_is_word_op,
+    output logic                   ex_is_branch,
+    output branch_op_t             ex_branch_op,
+    output logic                   ex_is_jump,
+
+    // Memory & Writeback Control
+    output logic                   ex_is_load,
+    output logic                   ex_is_store,
+    output logic [2:0]             ex_mem_size,
+    output logic                   ex_reg_write_en,
+    output logic [4:0]             ex_rd_addr,
+    output logic [1:0]             ex_wb_sel,
+
+    // System / Exception
+    output logic                   ex_is_csr,
+    output logic [2:0]             ex_csr_op,
+    output logic                   ex_illegal_instr,
+    output logic                   ex_is_ecall,
+    output logic                   ex_is_ebreak,
+    output logic                   ex_is_mret,
+    output logic                   ex_is_sret,
+    output logic                   ex_is_wfi,
+    output logic                   ex_is_sfence_vma,
+    output logic                   ex_is_fence,
+    output logic                   ex_is_fence_i
+);
+
+    always_ff @(posedge clk) begin
+        if (rst || flush_en) begin
+            ex_pc            <= '0;
+            ex_rs1_rdata     <= '0;
+            ex_rs2_rdata     <= '0;
+            ex_imm           <= '0;
+            ex_alu_op        <= ALU_ADD; // NOP is effectively ADD x0, x0, 0
+            ex_alu_src1_sel  <= '0;
+            ex_alu_src2_sel  <= '0;
+            ex_is_word_op    <= '0;
+            ex_is_branch     <= '0;
+            ex_branch_op     <= BRANCH_EQ;
+            ex_is_jump       <= '0;
+            ex_is_load       <= '0;
+            ex_is_store      <= '0;
+            ex_mem_size      <= '0;
+            ex_reg_write_en  <= '0; // VERY IMPORTANT: Do not write to regfile on NOP
+            ex_rd_addr       <= '0;
+            ex_wb_sel        <= '0;
+            ex_is_csr        <= '0;
+            ex_csr_op        <= '0;
+            ex_illegal_instr <= '0;
+            ex_is_ecall      <= '0;
+            ex_is_ebreak     <= '0;
+            ex_is_mret       <= '0;
+            ex_is_sret       <= '0;
+            ex_is_wfi        <= '0;
+            ex_is_sfence_vma <= '0;
+            ex_is_fence      <= '0;
+            ex_is_fence_i    <= '0;
+        end else if (~stall_en) begin
+            ex_pc            <= id_pc;
+            ex_rs1_rdata     <= id_rs1_rdata;
+            ex_rs2_rdata     <= id_rs2_rdata;
+            ex_imm           <= id_imm;
+            ex_alu_op        <= id_alu_op;
+            ex_alu_src1_sel  <= id_alu_src1_sel;
+            ex_alu_src2_sel  <= id_alu_src2_sel;
+            ex_is_word_op    <= id_is_word_op;
+            ex_is_branch     <= id_is_branch;
+            ex_branch_op     <= id_branch_op;
+            ex_is_jump       <= id_is_jump;
+            ex_is_load       <= id_is_load;
+            ex_is_store      <= id_is_store;
+            ex_mem_size      <= id_mem_size;
+            ex_reg_write_en  <= id_reg_write_en;
+            ex_rd_addr       <= id_rd_addr;
+            ex_wb_sel        <= id_wb_sel;
+            ex_is_csr        <= id_is_csr;
+            ex_csr_op        <= id_csr_op;
+            ex_illegal_instr <= id_illegal_instr;
+            ex_is_ecall      <= id_is_ecall;
+            ex_is_ebreak     <= id_is_ebreak;
+            ex_is_mret       <= id_is_mret;
+            ex_is_sret       <= id_is_sret;
+            ex_is_wfi        <= id_is_wfi;
+            ex_is_sfence_vma <= id_is_sfence_vma;
+            ex_is_fence      <= id_is_fence;
+            ex_is_fence_i    <= id_is_fence_i;
+        end
+        // If stall_en && !flush_en, maintain current state
+    end
+
+endmodule
diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt
index 5eb306e..e0a3238 100644
--- a/rv64cpu/tb/CMakeLists.txt
+++ b/rv64cpu/tb/CMakeLists.txt
@@ -94,6 +94,15 @@ add_verilator_target(
     INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
     TB_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_if_id_reg.cc
 )
+
+add_verilator_target(
+    NAME        tb_id_ex_reg
+    TOP_MODULE  id_ex_reg
+    SOURCES     ${RTL_CORE_DIR}/include/rv64_pkg.sv
+                ${RTL_CORE_DIR}/id_ex_reg.sv
+    INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
+    TB_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_id_ex_reg.cc
+)
 #
 # add_verilator_target(
 #     NAME        tb_csr
diff --git a/rv64cpu/tb/unit/tb_id_ex_reg.cc b/rv64cpu/tb/unit/tb_id_ex_reg.cc
new file mode 100644
index 0000000..ad58a87
--- /dev/null
+++ b/rv64cpu/tb/unit/tb_id_ex_reg.cc
@@ -0,0 +1,171 @@
+//     Richard CPU
+//     Copyright (C) 2026  Richard Qin
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+// File path: tb/unit/tb_id_ex_reg.cc
+// Description: ID/EX Pipeline Register unit test
+
+#include <iostream>
+#include <iomanip>
+#include <cstdint>
+#include <cassert>
+#include <verilated.h>
+#include "Vid_ex_reg.h"
+
+int pass_count = 0;
+
+void tick(Vid_ex_reg* dut) {
+    dut->clk = 0;
+    dut->eval();
+    dut->clk = 1;
+    dut->eval();
+    dut->clk = 0;
+    dut->eval();
+}
+
+void check(bool cond, const char* name) {
+    if (cond) {
+        std::cout << "\033[32m[PASS] " << name << "\033[0m" << std::endl;
+        pass_count++;
+    } else {
+        std::cout << "\033[31m[FAIL] " << name << "\033[0m" << std::endl;
+        assert(false);
+    }
+}
+
+// Emulate rv64_pkg::alu_op_t
+enum AluOp { ALU_ADD = 0, ALU_SUB = 8, ALU_SLL = 1, ALU_SLT = 2, ALU_SLTU = 3,
+             ALU_XOR = 4, ALU_SRL = 5, ALU_SRA = 13, ALU_OR = 6, ALU_AND = 7 };
+
+int main(int argc, char** argv) {
+    Verilated::commandArgs(argc, argv);
+    Vid_ex_reg* dut = new Vid_ex_reg;
+
+    std::cout << "----------------------------------" << std::endl;
+    std::cout << "        ID/EX Register Test" << std::endl;
+    std::cout << "----------------------------------" << std::endl;
+
+    // 1. Init / Reset
+    dut->stall_en = 0;
+    dut->flush_en = 0;
+    
+    // Set some random ID stage inputs with dangerous states
+    dut->id_pc = 0x80001000;
+    dut->id_rs1_rdata = 0x11111111;
+    dut->id_rs2_rdata = 0x22222222;
+    dut->id_imm = 0x1A2B3C;
+    dut->id_alu_op = ALU_XOR;
+    dut->id_reg_write_en = 1;
+    dut->id_is_store = 1;
+    dut->id_is_load = 1;
+    dut->id_is_branch = 1;
+    dut->id_is_jump = 1;
+    dut->id_is_csr = 1;
+    dut->id_illegal_instr = 1;
+
+    dut->rst = 1;
+    tick(dut);
+    dut->rst = 0;
+
+    // Verify reset clears out dangerous signals
+    check(dut->ex_pc == 0, "Reset_Clears_PC");
+    check(dut->ex_reg_write_en == 0, "Reset_Clears_RegWrite");
+    check(dut->ex_is_store == 0, "Reset_Clears_IsStore");
+    check(dut->ex_is_load == 0, "Reset_Clears_IsLoad");
+    check(dut->ex_is_branch == 0, "Reset_Clears_IsBranch");
+    check(dut->ex_is_jump == 0, "Reset_Clears_IsJump");
+    check(dut->ex_is_csr == 0, "Reset_Clears_IsCSR");
+    check(dut->ex_illegal_instr == 0, "Reset_Clears_IllegalInstr");
+
+    // 2. Normal Propagation
+    dut->id_pc = 0x80002000;
+    dut->id_rs1_rdata = 0xAAAAAAAA;
+    dut->id_rs2_rdata = 0xBBBBBBBB;
+    dut->id_imm = 42;
+    dut->id_alu_op = ALU_ADD;
+    dut->id_reg_write_en = 1;
+    dut->id_rd_addr = 5;
+    dut->id_is_load = 1;
+    dut->id_is_branch = 0;
+
+    tick(dut);
+
+    check(dut->ex_pc == 0x80002000, "Propagate_PC");
+    check(dut->ex_rs1_rdata == 0xAAAAAAAA, "Propagate_RS1");
+    check(dut->ex_rs2_rdata == 0xBBBBBBBB, "Propagate_RS2");
+    check(dut->ex_imm == 42, "Propagate_IMM");
+    check(dut->ex_alu_op == ALU_ADD, "Propagate_ALU_OP");
+    check(dut->ex_reg_write_en == 1, "Propagate_RegWriteEn");
+    check(dut->ex_rd_addr == 5, "Propagate_RdAddr");
+    check(dut->ex_is_load == 1, "Propagate_IsLoad");
+
+    // 3. Stall (Freeze)
+    // Change input, but assert stall
+    dut->stall_en = 1;
+    dut->id_pc = 0x80003000;
+    dut->id_rd_addr = 10;
+    dut->id_reg_write_en = 0;
+    dut->id_is_load = 0;
+    
+    tick(dut);
+
+    check(dut->ex_pc == 0x80002000, "Stall_Maintains_PC");
+    check(dut->ex_rd_addr == 5, "Stall_Maintains_RdAddr");
+    check(dut->ex_reg_write_en == 1, "Stall_Maintains_RegWriteEn");
+    check(dut->ex_is_load == 1, "Stall_Maintains_IsLoad");
+
+    // Release Stall
+    dut->stall_en = 0;
+    tick(dut);
+    check(dut->ex_pc == 0x80003000, "ReleaseStall_Captures_PC");
+    check(dut->ex_rd_addr == 10, "ReleaseStall_Captures_RdAddr");
+    check(dut->ex_reg_write_en == 0, "ReleaseStall_Captures_RegWriteEn");
+
+    // 4. Flush (Insert Bubble/NOP)
+    // Change input, but assert flush
+    dut->flush_en = 1;
+    dut->id_pc = 0x80004000;
+    dut->id_reg_write_en = 1;
+    dut->id_is_store = 1;
+    dut->id_is_branch = 1;
+    
+    tick(dut);
+
+    check(dut->ex_pc == 0x0, "Flush_Clears_PC");
+    check(dut->ex_reg_write_en == 0, "Flush_Clears_RegWrite"); 
+    check(dut->ex_is_store == 0, "Flush_Clears_StoreEn");     
+    check(dut->ex_is_branch == 0, "Flush_Clears_BranchEn");
+
+    // 5. Flush Overrides Stall
+    dut->flush_en = 0;
+    dut->id_pc = 0x80005000;
+    dut->id_reg_write_en = 1;
+    tick(dut); 
+    check(dut->ex_pc == 0x80005000, "Pre_FlushStall_Setup");
+
+    dut->flush_en = 1;
+    dut->stall_en = 1;
+    dut->id_pc = 0x80006000;
+    tick(dut);
+
+    check(dut->ex_pc == 0x0, "Flush_Overrides_Stall_PC");
+    check(dut->ex_reg_write_en == 0, "Flush_Overrides_Stall_RegWrite");
+
+    std::cout << "----------------------------------" << std::endl;
+    std::cout << "\033[32mAll " << pass_count << " tests passed!\033[0m" << std::endl;
+    std::cout << "----------------------------------" << std::endl;
+
+    delete dut;
+    return 0;
+}