refactor: standardize interrupt signal naming across the codebase

4 files changed, 36 insertions, 36 deletions

diff --git a/rv64cpu/rtl/core/mmu/tlb.sv b/rv64cpu/rtl/core/mmu/tlb.sv
index f466cb3..e4696fd 100644
--- a/rv64cpu/rtl/core/mmu/tlb.sv
+++ b/rv64cpu/rtl/core/mmu/tlb.sv
@@ -102,7 +102,7 @@ module tlb
 	logic [XLEN-1:0] low_mask;
 	logic        req_priv_u;
 	logic [XLEN-1:0] hit_ppn_xlen;
-	int unsigned shift_int;
+	int unsigned shift_index;
 
 	function automatic logic is_supported_mode(input logic [3:0] mode);
 		return (mode == SATP_MODE_BARE) || (mode == SATP_MODE_SV32) ||
@@ -248,7 +248,7 @@ module tlb
 		low_mask = '0;
 		req_priv_u = 1'b0;
 		hit_ppn_xlen = '0;
-		shift_int = 0;
+		shift_index = 0;
 
 		hit_found = 1'b0;
 		hit_ppn = '0;
@@ -286,11 +286,11 @@ module tlb
 
 				if (hit_found) begin
 					shift = page_shift(hit_mode, hit_level);
-					shift_int = int'(shift);
-					if (shift_int >= XLEN) begin
+					shift_index = int'(shift);
+					if (shift_index >= XLEN) begin
 						low_mask = {XLEN{1'b1}};
 					end else begin
-						low_mask = ({{(XLEN-1){1'b0}}, 1'b1} << shift_int) - 1;
+						low_mask = ({{(XLEN-1){1'b0}}, 1'b1} << shift_index) - 1;
 					end
 
 					hit_ppn_xlen = {{(XLEN-56){1'b0}}, hit_ppn, 12'b0};
diff --git a/rv64cpu/tb/core/tb_core.cc b/rv64cpu/tb/core/tb_core.cc
index b915df4..6877d8d 100644
--- a/rv64cpu/tb/core/tb_core.cc
+++ b/rv64cpu/tb/core/tb_core.cc
@@ -69,8 +69,8 @@ constexpr uint64_t EXC_STORE_FAULT  = 7ULL;
 constexpr uint64_t EXC_ECALL_FROM_U = 8ULL;
 constexpr uint64_t EXC_ECALL_FROM_M = 11ULL;
 constexpr uint64_t INTERRUPT_BIT    = 1ULL << 63;
-constexpr uint64_t INT_M_EXTERNAL   = 11ULL;
-constexpr uint64_t INT_M_TIMER      = 7ULL;
+constexpr uint64_t INTERRUPT_M_EXTERNAL   = 11ULL;
+constexpr uint64_t INTERRUPT_M_TIMER      = 7ULL;
 
 constexpr uint64_t LOG_ENTRY_STRIDE = 24ULL;
 constexpr uint64_t MACHINE_TRAP_VECTOR = 0x00000000ULL;
@@ -837,9 +837,9 @@ void test_fibonacci(CoreSim& sim) {
     
     for (int i = 0; i < 10; i++) {
         uint64_t addr = 0x10000000ULL + (i * 8);
-        uint64_t actual_val = sim.mem.read_data(addr); 
+        uint64_t actual_data = sim.mem.read_data(addr); 
         
-        ASSERT_EQ(actual_val, expected_fib[i], "Fibonacci value mismatch");
+        ASSERT_EQ(actual_data, expected_fib[i], "Fibonacci value mismatch");
     }
 }
 
@@ -949,7 +949,7 @@ static void run_branch_interrupt_priority_case() {
     emit_nops(boot, 8);
     emit_csrrw_imm64(boot, 1, CSR_MTVEC, MACHINE_TRAP_VECTOR);
     emit_csrrw_imm64(boot, 2, CSR_MSTATUS, (1ULL << MSTATUS_MIE_BIT));
-    emit_csrrw_imm64(boot, 3, CSR_MIE, (1ULL << INT_M_EXTERNAL));
+    emit_csrrw_imm64(boot, 3, CSR_MIE, (1ULL << INTERRUPT_M_EXTERNAL));
     boot.push_back(JAL(0, 0));
     sim.mem.load_program(boot_pc, boot);
 
@@ -961,7 +961,7 @@ static void run_branch_interrupt_priority_case() {
     sim.run(20);
 
     const TrapRecord interrupt_trap = fetch_trap_record(sim.mem, log_base, 0);
-    ASSERT_EQ(interrupt_trap.mcause, INTERRUPT_BIT | INT_M_EXTERNAL, "external interrupt cause");
+    ASSERT_EQ(interrupt_trap.mcause, INTERRUPT_BIT | INTERRUPT_M_EXTERNAL, "external interrupt cause");
     ASSERT_EQ(interrupt_trap.mtval, 0ULL, "interrupt mtval should be zero");
 }
 
@@ -980,7 +980,7 @@ static void run_mie_masking_case() {
     std::vector<uint32_t> program;
     emit_nops(program, 8);
     emit_csrrw_imm64(program, 1, CSR_MTVEC, MACHINE_TRAP_VECTOR);
-    emit_csrrw_imm64(program, 2, CSR_MIE, (1ULL << INT_M_EXTERNAL));
+    emit_csrrw_imm64(program, 2, CSR_MIE, (1ULL << INTERRUPT_M_EXTERNAL));
     program.push_back(CSRRW(0, CSR_MSTATUS, 0));
     emit_nops(program, 8);
     emit_nops(program, 48);
@@ -994,8 +994,8 @@ static void run_mie_masking_case() {
     sim.run(20);
     ASSERT_EQ(sim.mem.read_data(log_base), 0ULL, "no trap while MIE=0");
     sim.run(100);
-    const TrapRecord int_trap = fetch_trap_record(sim.mem, log_base, 0);
-    ASSERT_EQ(int_trap.mcause, INTERRUPT_BIT | INT_M_EXTERNAL, "external interrupt cause");
+    const TrapRecord interrupt_trap = fetch_trap_record(sim.mem, log_base, 0);
+    ASSERT_EQ(interrupt_trap.mcause, INTERRUPT_BIT | INTERRUPT_M_EXTERNAL, "external interrupt cause");
 }
 
 // TODO: Add EXPECT_FAIL once trap_load_page_fault/trap_store_page_fault are driven by the MMU.
diff --git a/rv64cpu/tb/unit/tb_csr.cc b/rv64cpu/tb/unit/tb_csr.cc
index 9dce96f..8391759 100644
--- a/rv64cpu/tb/unit/tb_csr.cc
+++ b/rv64cpu/tb/unit/tb_csr.cc
@@ -66,9 +66,9 @@ constexpr uint64_t EXC_LOAD_FAULT   = 5ULL;
 constexpr uint64_t EXC_STORE_FAULT  = 7ULL;
 
 constexpr uint64_t INTERRUPT_BIT    = 1ULL << 63;
-constexpr uint64_t INT_M_SOFTWARE   = 3ULL;
-constexpr uint64_t INT_M_TIMER      = 7ULL;
-constexpr uint64_t INT_M_EXTERNAL   = 11ULL;
+constexpr uint64_t INTERRUPT_M_SOFTWARE   = 3ULL;
+constexpr uint64_t INTERRUPT_M_TIMER      = 7ULL;
+constexpr uint64_t INTERRUPT_M_EXTERNAL   = 11ULL;
 
 constexpr int MSTATUS_MIE_BIT  = 3;
 constexpr int MSTATUS_MPIE_BIT = 7;
@@ -145,8 +145,8 @@ void trigger_trap(
     dut->trap_ctrl_to_s_mode = 0;
 }
 
-void trigger_interrupt(Vcsr_unit* dut, uint64_t mepc, uint64_t int_cause) {
-    trigger_trap(dut, mepc, (INTERRUPT_BIT | int_cause), 0ULL, false);
+void trigger_interrupt(Vcsr_unit* dut, uint64_t mepc, uint64_t interrupt_cause) {
+    trigger_trap(dut, mepc, (INTERRUPT_BIT | interrupt_cause), 0ULL, false);
 }
 
 template <typename Fn>
@@ -204,15 +204,15 @@ uint64_t arbitrate_trap_priority(
 ) {
     if (ext_external) {
         chose_interrupt = true;
-        return INTERRUPT_BIT | INT_M_EXTERNAL;
+        return INTERRUPT_BIT | INTERRUPT_M_EXTERNAL;
     }
     if (ext_software) {
         chose_interrupt = true;
-        return INTERRUPT_BIT | INT_M_SOFTWARE;
+        return INTERRUPT_BIT | INTERRUPT_M_SOFTWARE;
     }
     if (ext_timer) {
         chose_interrupt = true;
-        return INTERRUPT_BIT | INT_M_TIMER;
+        return INTERRUPT_BIT | INTERRUPT_M_TIMER;
     }
     chose_interrupt = false;
     return has_sync_exception ? sync_cause : 0ULL;
@@ -393,10 +393,10 @@ int main(int argc, char** argv) {
         };
 
         const std::array<PriorityScenario, 5> suite = {{
-            {"external_over_others", true,  true,  true,  true,  0xA000ULL, 0x1111ULL, INTERRUPT_BIT | INT_M_EXTERNAL},
-            {"software_over_timer",  false, true,  true,  true,  0xA040ULL, 0x2222ULL, INTERRUPT_BIT | INT_M_SOFTWARE},
-            {"timer_over_sync",      false, false, true,  true,  0xA080ULL, 0x3333ULL, INTERRUPT_BIT | INT_M_TIMER},
-            {"interrupt_only",       true,  false, false, false, 0xA0C0ULL, 0x0ULL,     INTERRUPT_BIT | INT_M_EXTERNAL},
+            {"external_over_others", true,  true,  true,  true,  0xA000ULL, 0x1111ULL, INTERRUPT_BIT | INTERRUPT_M_EXTERNAL},
+            {"software_over_timer",  false, true,  true,  true,  0xA040ULL, 0x2222ULL, INTERRUPT_BIT | INTERRUPT_M_SOFTWARE},
+            {"timer_over_sync",      false, false, true,  true,  0xA080ULL, 0x3333ULL, INTERRUPT_BIT | INTERRUPT_M_TIMER},
+            {"interrupt_only",       true,  false, false, false, 0xA0C0ULL, 0x0ULL,     INTERRUPT_BIT | INTERRUPT_M_EXTERNAL},
             {"sync_fallback",        false, false, false, true,  0xA100ULL, 0x4444ULL, EXC_INST_ILLEGAL}
         }};
 
@@ -535,8 +535,8 @@ int main(int argc, char** argv) {
         const std::array<DelegationProbe, 4> probes = {{
             {"medeleg_set",   false, EXC_ECALL_FROM_U, true,  0xD000ULL},
             {"medeleg_clear", false, EXC_ECALL_FROM_U, false, 0xD040ULL},
-            {"mideleg_set",   true,  INT_M_TIMER,      true,  0xD080ULL},
-            {"mideleg_clear", true,  INT_M_TIMER,      false, 0xD0C0ULL}
+            {"mideleg_set",   true,  INTERRUPT_M_TIMER,      true,  0xD080ULL},
+            {"mideleg_clear", true,  INTERRUPT_M_TIMER,      false, 0xD0C0ULL}
         }};
 
         for (const auto& probe : probes) {
diff --git a/rv64cpu/tb/unit/tb_trap_ctrl.cc b/rv64cpu/tb/unit/tb_trap_ctrl.cc
index 29d3439..f0b667c 100644
--- a/rv64cpu/tb/unit/tb_trap_ctrl.cc
+++ b/rv64cpu/tb/unit/tb_trap_ctrl.cc
@@ -32,9 +32,9 @@ constexpr uint64_t EXC_STORE_PAGE_FAULT= 15ULL;
 constexpr uint64_t EXC_LOAD_FAULT     = 5ULL;
 constexpr uint64_t EXC_STORE_FAULT    = 7ULL;
 
-constexpr uint64_t INT_M_SOFTWARE     = 3ULL;
-constexpr uint64_t INT_M_TIMER        = 7ULL;
-constexpr uint64_t INT_M_EXTERNAL     = 11ULL;
+constexpr uint64_t INTERRUPT_M_SOFTWARE = 3ULL;
+constexpr uint64_t INTERRUPT_M_TIMER    = 7ULL;
+constexpr uint64_t INTERRUPT_M_EXTERNAL = 11ULL;
 
 constexpr uint64_t INTERRUPT_BIT      = 1ULL << 63;
 constexpr uint64_t PRIV_MODE_U        = 0ULL;
@@ -161,9 +161,9 @@ int main(int argc, char** argv) {
     dut->ext_software_interrupt = 1;
     dut->ext_external_interrupt = 1;
     dut->eval();
-    const uint64_t expected_vectored_pc = 0x300ULL + (INT_M_EXTERNAL << 2);
+    const uint64_t expected_vectored_pc = 0x300ULL + (INTERRUPT_M_EXTERNAL << 2);
     check(dut->trap_trigger, "InterruptPriority_Triggers");
-    check(dut->trap_mcause == (INTERRUPT_BIT | INT_M_EXTERNAL), "InterruptPriority_Mcause");
+    check(dut->trap_mcause == (INTERRUPT_BIT | INTERRUPT_M_EXTERNAL), "InterruptPriority_Mcause");
     check(dut->trap_mtval == 0ULL, "InterruptPriority_MtvalZero");
     check(dut->trap_next_pc == expected_vectored_pc, "InterruptPriority_VectoredJump");
 
@@ -177,14 +177,14 @@ int main(int argc, char** argv) {
     dut->csr_priv_mode = PRIV_MODE_S;
     dut->csr_mstatus_mie = 1;
     dut->csr_stvec = 0x880ULL | 0x1ULL;  // vectored supervisor mode
-    dut->csr_mideleg = (1ULL << INT_M_TIMER);
+    dut->csr_mideleg = (1ULL << INTERRUPT_M_TIMER);
     dut->wb_pc = 0xABCDULL;
     dut->ext_timer_interrupt = 1;
     dut->eval();
-    const uint64_t expected_sv_pc = 0x880ULL + (INT_M_TIMER << 2);
+    const uint64_t expected_sv_pc = 0x880ULL + (INTERRUPT_M_TIMER << 2);
     check(dut->trap_to_s_mode, "InterruptDelegation_ToSupervisor");
     check(dut->trap_next_pc == expected_sv_pc, "InterruptDelegation_UsesStvec");
-    check(dut->trap_mcause == (INTERRUPT_BIT | INT_M_TIMER), "InterruptDelegation_Mcause");
+    check(dut->trap_mcause == (INTERRUPT_BIT | INTERRUPT_M_TIMER), "InterruptDelegation_Mcause");
 
     // ---------------------------------------------------------------------
     // 3) MRET/SRET redirect without new traps