diff options
| -rw-r--r-- | backend/lib/Target/RISCV/RISCV.rccdesc | 30 | ||||
| -rw-r--r-- | backend/unittests/Target/RISCVTargetTest.cpp | 32 |
2 files changed, 47 insertions, 15 deletions
diff --git a/backend/lib/Target/RISCV/RISCV.rccdesc b/backend/lib/Target/RISCV/RISCV.rccdesc index 8325777..7872212 100644 --- a/backend/lib/Target/RISCV/RISCV.rccdesc +++ b/backend/lib/Target/RISCV/RISCV.rccdesc @@ -789,7 +789,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 1 flags: [may_load, produces_code] scheduling_class: LOAD @@ -805,7 +805,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 1 flags: [may_load, produces_code] scheduling_class: LOAD @@ -821,7 +821,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 1 flags: [may_load, produces_code] scheduling_class: LOAD @@ -837,7 +837,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 1 flags: [may_load, produces_code] scheduling_class: LOAD @@ -853,7 +853,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 1 flags: [may_load, produces_code] scheduling_class: LOAD @@ -869,7 +869,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 1 flags: [may_load, produces_code] scheduling_class: LOAD @@ -885,7 +885,7 @@ instructions: operands: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 0 flags: [may_store, produces_code] scheduling_class: STORE @@ -901,7 +901,7 @@ instructions: operands: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 0 flags: [may_store, produces_code] scheduling_class: STORE @@ -917,7 +917,7 @@ instructions: operands: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 0 flags: [may_store, produces_code] scheduling_class: STORE @@ -1351,7 +1351,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 1 flags: [may_load, produces_code] scheduling_class: LOAD @@ -1367,7 +1367,7 @@ instructions: operands: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 0 flags: [may_store, produces_code] scheduling_class: STORE @@ -1588,7 +1588,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, memory_role: value, name: FRD } - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 1 flags: [may_load, produces_code] scheduling_class: LOAD @@ -1604,7 +1604,7 @@ instructions: operands: - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, memory_role: value, name: FRS2 } - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 0 flags: [may_store, produces_code] scheduling_class: STORE @@ -2066,7 +2066,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRD } - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 1 flags: [may_load, produces_code] scheduling_class: LOAD @@ -2082,7 +2082,7 @@ instructions: operands: - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRS2 } - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } num_explicit_defs: 0 flags: [may_store, produces_code] scheduling_class: STORE diff --git a/backend/unittests/Target/RISCVTargetTest.cpp b/backend/unittests/Target/RISCVTargetTest.cpp index 4e36e1e..1926d0a 100644 --- a/backend/unittests/Target/RISCVTargetTest.cpp +++ b/backend/unittests/Target/RISCVTargetTest.cpp @@ -5,6 +5,7 @@ #include "rcc/CodeGen/GenericOpcodes.h" #include <algorithm> +#include <array> #include <cstddef> #include <cstdint> #include <iostream> @@ -191,6 +192,37 @@ void testInstructionFacts(TestContext &Context) { rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::ADDI))); const auto *FenceAssembly = rcc::riscv::assemblyInstruction( rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::FENCE_I))); + + constexpr std::array SymbolicLowOpcodes = { + rcc::riscv::InstructionOpcode::LB, rcc::riscv::InstructionOpcode::LH, + rcc::riscv::InstructionOpcode::LW, rcc::riscv::InstructionOpcode::LBU, + rcc::riscv::InstructionOpcode::LHU, rcc::riscv::InstructionOpcode::LWU, + rcc::riscv::InstructionOpcode::SB, rcc::riscv::InstructionOpcode::SH, + rcc::riscv::InstructionOpcode::SW, rcc::riscv::InstructionOpcode::LD, + rcc::riscv::InstructionOpcode::SD, rcc::riscv::InstructionOpcode::FLW, + rcc::riscv::InstructionOpcode::FSW, rcc::riscv::InstructionOpcode::FLD, + rcc::riscv::InstructionOpcode::FSD, + }; + const rcc::OperandKindSet SymbolicLowKinds = { + rcc::MachineOperand::Kind::Immediate, rcc::MachineOperand::Kind::ConstantPoolIndex, + rcc::MachineOperand::Kind::JumpTableIndex, rcc::MachineOperand::Kind::GlobalSymbol, + rcc::MachineOperand::Kind::ExternalSymbol, rcc::MachineOperand::Kind::BlockAddress, + rcc::MachineOperand::Kind::MCSymbol, + }; + Context.expect( + Load != nullptr && Load->Operands.size() == 3 && + std::ranges::all_of(SymbolicLowOpcodes, + [&](rcc::riscv::InstructionOpcode Opcode) { + const auto *Descriptor = Target->instructionDescriptor( + rcc::Opcode::fromValue(static_cast<std::uint32_t>(Opcode))); + return Descriptor != nullptr && Descriptor->Operands.size() == 3 && + Descriptor->Operands[2].Kinds == SymbolicLowKinds && + Descriptor->Operands[2].ImmediatePredicate == + Load->Operands[2].ImmediatePredicate && + Descriptor->Operands[2].AllowedTargetFlags == 68; + }), + "RV64GC loads and stores must accept SIMM12 low-part symbolic operands"); + Context.expect( Target->instructions().descriptors().size() == TargetInstructionCount + rcc::genericInstructionDescriptors().size() && |