3 files changed, 29 insertions, 21 deletions
diff --git a/backend/include/rcc/CodeGen/GlobalISel/LegalizerHelper.h b/backend/include/rcc/CodeGen/GlobalISel/LegalizerHelper.h
index 19b3345..07ee8bb 100644
--- a/backend/include/rcc/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/backend/include/rcc/CodeGen/GlobalISel/LegalizerHelper.h
@@ -28,6 +28,7 @@ public:
                                         const LegalizationDecision &Decision);
   [[nodiscard]] Expected<void> lower(MachineInstr &Instruction,
                                      const LegalizationDecision &Decision);
+  [[nodiscard]] Expected<void> lowerAbsToAddXor(MachineInstr &Instruction);
   [[nodiscard]] Expected<void> lowerVAArg(MachineInstr &Instruction);
   [[nodiscard]] Expected<void> widenScalar(MachineInstr &Instruction, std::size_t TypeIndex,
                                            LowLevelType WideType);
diff --git a/backend/include/rcc/CodeGen/GlobalISel/LegalizerInfo.h b/backend/include/rcc/CodeGen/GlobalISel/LegalizerInfo.h
index 9162526..2981f8e 100644
--- a/backend/include/rcc/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/backend/include/rcc/CodeGen/GlobalISel/LegalizerInfo.h
@@ -24,6 +24,7 @@ class MachineFunction;
 class MachineInstr;
 class TargetDescription;
 class LegalizerHelper;
+enum class GenericOpcode : std::uint32_t;
 
 enum class LegalizationAction : std::uint8_t {
   Legal,
@@ -181,6 +182,8 @@ public:
     return true;
   }
 
+  [[nodiscard]] virtual GenericOpcode getExtOpcodeForWideningConstant(LowLevelType SmallType) const;
+
   // This hook performs read-only target checks before a lowering mutation is committed.
   [[nodiscard]] virtual Expected<void> validateLowering(const MachineInstr &,
                                                         const MachineFunction &,
diff --git a/backend/include/rcc/CodeGen/GlobalISel/Utils.h b/backend/include/rcc/CodeGen/GlobalISel/Utils.h
index 5af2fb4..f252454 100644
--- a/backend/include/rcc/CodeGen/GlobalISel/Utils.h
+++ b/backend/include/rcc/CodeGen/GlobalISel/Utils.h
@@ -3,11 +3,13 @@
 #ifndef RCC_CODEGEN_GLOBALISEL_UTILS_H
 #define RCC_CODEGEN_GLOBALISEL_UTILS_H
 
+#include "rcc/ADT/APInt.h"
 #include "rcc/CodeGen/LowLevelType.h"
 #include "rcc/CodeGen/Register.h"
 #include "rcc/Support/Error.h"
 
 #include <cstddef>
+#include <optional>
 #include <span>
 #include <vector>
 
@@ -18,36 +20,38 @@ class MachineInstr;
 class MachineRegisterInfo;
 class TargetDescription;
 
+struct ValueAndVReg final {
+  APInt Value;
+  Register VReg;
+};
+
+[[nodiscard]] std::optional<ValueAndVReg>
+getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
+                                   bool LookThroughInstrs = true);
+
 /// Check whether an instruction only defines dead virtual registers and has no
 /// observable side effects.
-[[nodiscard]] bool isTriviallyDead(const MachineInstr &Instruction,
-                                   const MachineRegisterInfo &MRI,
+[[nodiscard]] bool isTriviallyDead(const MachineInstr &Instruction, const MachineRegisterInfo &MRI,
                                    const TargetDescription &Target) noexcept;
 
 [[nodiscard]] Expected<void> eraseInstrs(std::span<MachineInstr *const> Instructions,
-                                         MachineRegisterInfo &MRI,
-                                         const TargetDescription &Target);
+                                         MachineRegisterInfo &MRI, const TargetDescription &Target);
 
-[[nodiscard]] Expected<void> eraseInstr(MachineInstr &Instruction,
-                                        MachineRegisterInfo &MRI,
+[[nodiscard]] Expected<void> eraseInstr(MachineInstr &Instruction, MachineRegisterInfo &MRI,
                                         const TargetDescription &Target);
 
-[[nodiscard]] Expected<void> extractParts(Register Reg, LowLevelType Type,
-                                          int PartCount,
+[[nodiscard]] Expected<void> extractParts(Register Reg, LowLevelType Type, int PartCount,
                                           std::vector<Register> &Parts,
-                                          MachineIRBuilder &MIRBuilder,
-                                          MachineRegisterInfo &MRI);
-
-[[nodiscard]] Expected<bool>
-extractParts(Register Reg, LowLevelType RegisterType, LowLevelType MainType,
-             LowLevelType &LeftoverType, std::vector<Register> &Parts,
-             std::vector<Register> &LeftoverParts,
-             MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI);
-
-[[nodiscard]] Expected<LowLevelType> getLCMType(LowLevelType OriginalType,
-                                                LowLevelType TargetType);
-[[nodiscard]] Expected<LowLevelType> getGCDType(LowLevelType OriginalType,
-                                                LowLevelType TargetType);
+                                          MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI);
+
+[[nodiscard]] Expected<bool> extractParts(Register Reg, LowLevelType RegisterType,
+                                          LowLevelType MainType, LowLevelType &LeftoverType,
+                                          std::vector<Register> &Parts,
+                                          std::vector<Register> &LeftoverParts,
+                                          MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI);
+
+[[nodiscard]] Expected<LowLevelType> getLCMType(LowLevelType OriginalType, LowLevelType TargetType);
+[[nodiscard]] Expected<LowLevelType> getGCDType(LowLevelType OriginalType, LowLevelType TargetType);
 
 } // namespace rcc