2 files changed, 10 insertions, 0 deletions
diff --git a/backend/include/rcc/Target/RISCV/RISCVPipeline.h b/backend/include/rcc/Target/RISCV/RISCVPipeline.h
index 262f7c1..21a4461 100644
--- a/backend/include/rcc/Target/RISCV/RISCVPipeline.h
+++ b/backend/include/rcc/Target/RISCV/RISCVPipeline.h
@@ -24,6 +24,7 @@ struct RISCVPipelineOptions final {
   OptimizationLevel Optimization = OptimizationLevel::O2;
   bool UseTargetCopyInstructions = false;
   GlobalISelAbortMode GlobalISelAbort = GlobalISelAbortMode::Enable;
+  bool DebugMachineScheduler = false;
 };
 
 [[nodiscard]] Expected<void> addCanonicalPipeline(MachineFunctionPassManager &Pipeline,
diff --git a/backend/include/rcc/Target/RISCV/RISCVSubtarget.h b/backend/include/rcc/Target/RISCV/RISCVSubtarget.h
index a77a045..c8a4298 100644
--- a/backend/include/rcc/Target/RISCV/RISCVSubtarget.h
+++ b/backend/include/rcc/Target/RISCV/RISCVSubtarget.h
@@ -10,12 +10,15 @@
 #include <memory>
 #include <span>
 #include <string>
+#include <string_view>
 
 namespace rcc {
 
 class InstructionSelector;
 class LegalizerInfo;
 class TargetCallLowering;
+class TargetSchedulingHooks;
+class TargetSchedulingModel;
 
 namespace riscv {
 
@@ -45,6 +48,7 @@ enum class RISCVSubtargetOption : std::uint8_t {
   FusionAddImmediateLoad,
   FusionAUIPCAddImmediate,
   FusionAUIPCLoad,
+  FusionBitfieldExtract,
   FusionLoadDoubleAdd,
   FusionLogicImmediateRegister,
   FusionLogicRegisterImmediate,
@@ -53,6 +57,7 @@ enum class RISCVSubtargetOption : std::uint8_t {
   FusionLUILoad,
   FusionMultiplyAdd,
   FusionShiftBitExtract,
+  FusionShiftedAddLoad,
   FusionShiftedZeroExtendWord,
   FusionZeroExtendHalf,
   FusionZeroExtendWord,
@@ -74,6 +79,7 @@ public:
 
   [[nodiscard]] bool has(RISCVExtension Extension) const noexcept;
   [[nodiscard]] bool has(RISCVSubtargetOption Option) const noexcept;
+  [[nodiscard]] bool hasFeature(std::string_view Feature) const noexcept;
 
   friend bool operator==(const RISCVSubtargetFeatures &Left,
                          const RISCVSubtargetFeatures &Right) = default;
@@ -114,6 +120,7 @@ public:
   [[nodiscard]] InstructionSelector *getInstructionSelector() const;
   [[nodiscard]] const LegalizerInfo *getLegalizerInfo() const;
   [[nodiscard]] const RISCVRegisterBankInfo *getRegBankInfo() const;
+  [[nodiscard]] const TargetSchedulingModel &schedulingModel() const noexcept;
 
 private:
   RISCVSubtargetFeatures Features;
@@ -123,6 +130,8 @@ private:
   mutable std::unique_ptr<InstructionSelector> InstSelector;
   mutable std::unique_ptr<LegalizerInfo> Legalizer;
   mutable std::unique_ptr<RISCVRegisterBankInfo> RegBankInfo;
+  std::unique_ptr<TargetSchedulingHooks> SchedulingHooks;
+  std::unique_ptr<TargetSchedulingModel> SchedulingModel;
 };
 
 } // namespace riscv