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-rw-r--r--backend/lib/CodeGen/MachineCombiner.cpp18
-rw-r--r--backend/lib/CodeGen/MachinePipelinePasses.cpp18
-rw-r--r--backend/lib/Target/RISCV/RISCVPipeline.cpp13
-rw-r--r--backend/lib/Tooling/BackendDriver.cpp9
-rw-r--r--backend/lib/Tooling/PipelineDriver.cpp6
5 files changed, 45 insertions, 19 deletions
diff --git a/backend/lib/CodeGen/MachineCombiner.cpp b/backend/lib/CodeGen/MachineCombiner.cpp
index 54915ab..9a87b6f 100644
--- a/backend/lib/CodeGen/MachineCombiner.cpp
+++ b/backend/lib/CodeGen/MachineCombiner.cpp
@@ -25,6 +25,20 @@ namespace rcc {
namespace {
[[nodiscard]] const MachinePassContract &combinerContract(MachineCombinerStage Stage) {
+ static const MachinePassContract PreLegalizer = [] {
+ MachinePassContract Value{
+ .Name = "riscv-prelegalizer-combiner",
+ .Requires = {MachineFunctionProperty::IsSSA},
+ .Sets = {},
+ .Clears = {},
+ .RequiredAnalyses = {},
+ .VerificationStage = PipelineStage::MachineIRInput,
+ };
+ Value.ThreadSafety = PassThreadSafety::ThreadSafe;
+ Value.DeclaredChanges = {MachinePassChange::Instructions, MachinePassChange::Operands,
+ MachinePassChange::Registers};
+ return Value;
+ }();
static const MachinePassContract SelectedSSA = [] {
MachinePassContract Value{
.Name = "machine-combiner-selected-ssa",
@@ -85,6 +99,8 @@ namespace {
return Value;
}();
switch (Stage) {
+ case MachineCombinerStage::PreLegalizer:
+ return PreLegalizer;
case MachineCombinerStage::SelectedSSA:
return SelectedSSA;
case MachineCombinerStage::PreRegisterAllocation:
@@ -94,7 +110,7 @@ namespace {
case MachineCombinerStage::PostFrame:
return PostFrame;
}
- return SelectedSSA;
+ return PreLegalizer;
}
[[nodiscard]] Error prefixedError(const Error &Failure, std::string Prefix) {
diff --git a/backend/lib/CodeGen/MachinePipelinePasses.cpp b/backend/lib/CodeGen/MachinePipelinePasses.cpp
index 9bde291..3dae07e 100644
--- a/backend/lib/CodeGen/MachinePipelinePasses.cpp
+++ b/backend/lib/CodeGen/MachinePipelinePasses.cpp
@@ -24,7 +24,7 @@ namespace {
[[nodiscard]] const MachinePassContract &legalizerContract() {
static const MachinePassContract Contract{
- .Name = "Legalizer",
+ .Name = "legalizer",
// LLVM's GlobalISel legalizer operates on SSA form and does not require
// the optional register-liveness tracking property.
.Requires = {MachineFunctionProperty::IsSSA},
@@ -38,7 +38,7 @@ namespace {
[[nodiscard]] const MachinePassContract &bankSelectContract() {
static const MachinePassContract Contract{
- .Name = "RegisterBankSelect",
+ .Name = "regbankselect",
.Requires = {MachineFunctionProperty::Legalized},
.Sets = {MachineFunctionProperty::RegBankSelected},
.Clears = {},
@@ -50,7 +50,7 @@ namespace {
[[nodiscard]] const MachinePassContract &instructionSelectContract() {
static const MachinePassContract Contract{
- .Name = "InstructionSelect",
+ .Name = "instruction-select",
.Requires = {MachineFunctionProperty::Legalized, MachineFunctionProperty::RegBankSelected},
.Sets = {MachineFunctionProperty::Selected},
.Clears = {},
@@ -281,8 +281,7 @@ registerConfigurationFingerprint(const MachineRegisterInfo &RegInfo) noexcept {
[[nodiscard]] Expected<void> clearTrackedLivenessFlags(MachineFunction &Function,
MachinePassResult &Result) {
- if (!Result.Changed ||
- !Function.properties().has(MachineFunctionProperty::TracksLiveness))
+ if (!Result.Changed || !Function.properties().has(MachineFunctionProperty::TracksLiveness))
return {};
bool Changed = false;
for (MachineInstr *Instruction : layoutInstructions(Function)) {
@@ -291,8 +290,7 @@ registerConfigurationFingerprint(const MachineRegisterInfo &RegInfo) noexcept {
if (!Operand.isRegister())
continue;
RegisterOperandFlags Flags = Operand.registerFlags();
- if (!Flags.has(RegisterOperandFlag::Kill) &&
- !Flags.has(RegisterOperandFlag::Dead))
+ if (!Flags.has(RegisterOperandFlag::Kill) && !Flags.has(RegisterOperandFlag::Dead))
continue;
Flags.clear(RegisterOperandFlag::Kill);
Flags.clear(RegisterOperandFlag::Dead);
@@ -413,9 +411,9 @@ Expected<MachinePassResult> LegalizerPass::runImplementation(MachineFunction &Fu
if (!InstructionWasErased) {
const OpcodeState After = stateOf(*Instruction);
if (After == Before)
- return std::unexpected(passFailure(
- "target legalizer made no observable progress for '" + Descriptor->Name + "'",
- ErrorCode::InternalError));
+ return std::unexpected(passFailure("target legalizer made no observable progress for '" +
+ Descriptor->Name + "'",
+ ErrorCode::InternalError));
}
Result.Changed = true;
Result.Changes.add(MachinePassChange::Instructions);
diff --git a/backend/lib/Target/RISCV/RISCVPipeline.cpp b/backend/lib/Target/RISCV/RISCVPipeline.cpp
index 05d26b3..d995060 100644
--- a/backend/lib/Target/RISCV/RISCVPipeline.cpp
+++ b/backend/lib/Target/RISCV/RISCVPipeline.cpp
@@ -2,6 +2,7 @@
#include "rcc/Target/RISCV/RISCVPipeline.h"
+#include "rcc/CodeGen/MachineCombiner.h"
#include "rcc/CodeGen/MachineFunction.h"
#include "rcc/CodeGen/MachineOptimizationPipeline.h"
#include "rcc/CodeGen/MachinePipelinePasses.h"
@@ -27,7 +28,11 @@ template <typename PassT, typename... ArgumentT>
[[nodiscard]] Expected<void> addInitialPipeline(MachinePassManager &Pipeline,
RISCVSubtargetFeatures Features) {
- auto Added = addPass<LegalizerPass>(Pipeline, createLegalizerInfo(Features));
+ auto Added = addPass<MachineCombinerPass>(Pipeline, machineCombinerInfo(),
+ MachineCombinerStage::PreLegalizer);
+ if (!Added)
+ return std::unexpected(Added.error());
+ Added = addPass<LegalizerPass>(Pipeline, createLegalizerInfo(Features));
if (!Added)
return std::unexpected(Added.error());
Added = addPass<RegisterBankSelectPass>(Pipeline, registerBankInfo());
@@ -76,7 +81,11 @@ Expected<void> addCanonicalPipeline(MachinePassManager &Pipeline, const MachineF
Expected<void> addCanonicalPipeline(MachinePassManager &Pipeline, const MachineFunction &Function,
RISCVSubtargetFeatures Features) {
if (!Function.properties().has(MachineFunctionProperty::Legalized)) {
- auto Added = addPass<LegalizerPass>(Pipeline, createLegalizerInfo(Features));
+ auto Added = addPass<MachineCombinerPass>(Pipeline, machineCombinerInfo(),
+ MachineCombinerStage::PreLegalizer);
+ if (!Added)
+ return std::unexpected(Added.error());
+ Added = addPass<LegalizerPass>(Pipeline, createLegalizerInfo(Features));
if (!Added)
return std::unexpected(Added.error());
}
diff --git a/backend/lib/Tooling/BackendDriver.cpp b/backend/lib/Tooling/BackendDriver.cpp
index 2a2a500..fff58c5 100644
--- a/backend/lib/Tooling/BackendDriver.cpp
+++ b/backend/lib/Tooling/BackendDriver.cpp
@@ -49,9 +49,10 @@ namespace {
[[nodiscard]] Expected<std::vector<std::uint8_t>> printMIR(const mir::MIRDocument &Document,
const TargetDescription &Target,
- const BackendInvocation &Invocation) {
+ const BackendInvocation &Invocation,
+ bool Simplify) {
mir::MIRDocumentPrinterOptions Options;
- Options.Mode = mir::MIPrintMode::Complete;
+ Options.Mode = Simplify ? mir::MIPrintMode::Readable : mir::MIPrintMode::Complete;
Options.EmitEmbeddedIR = true;
Options.DataLayout = Invocation.DataLayout;
auto Printed = mir::printMIRDocument(Document, Target, std::move(Options));
@@ -103,6 +104,8 @@ Expected<BackendRunResult> runBackend(CanonicalMIR Input, const TargetDescriptio
Controls.StopAtStage = RequiredStage;
}
+ const bool SimplifyMIR = Controls.SimplifyMIR;
+
MachinePassInstrumentation LocalInstrumentation;
MachinePassInstrumentation *ActiveInstrumentation =
Instrumentation == nullptr ? &LocalInstrumentation : Instrumentation;
@@ -113,7 +116,7 @@ Expected<BackendRunResult> runBackend(CanonicalMIR Input, const TargetDescriptio
std::vector<std::uint8_t> Bytes;
if (isMIR(Output)) {
- auto Printed = printMIR(Input.Document, Target, Invocation);
+ auto Printed = printMIR(Input.Document, Target, Invocation, SimplifyMIR);
if (!Printed)
return std::unexpected(Printed.error());
Bytes = std::move(*Printed);
diff --git a/backend/lib/Tooling/PipelineDriver.cpp b/backend/lib/Tooling/PipelineDriver.cpp
index 4dab499..620367f 100644
--- a/backend/lib/Tooling/PipelineDriver.cpp
+++ b/backend/lib/Tooling/PipelineDriver.cpp
@@ -55,11 +55,11 @@ struct FunctionRunResult final {
}
[[nodiscard]] std::optional<BackendStage> stageAfterPass(std::string_view Pass) noexcept {
- if (Pass == "Legalizer")
+ if (Pass == "legalizer")
return BackendStage::LegalizedMIR;
- if (Pass == "RegisterBankSelect")
+ if (Pass == "regbankselect")
return BackendStage::RegisterBankMIR;
- if (Pass == "InstructionSelect")
+ if (Pass == "instruction-select")
return BackendStage::SelectedMIR;
if (Pass == "TwoAddressRewrite")
return BackendStage::PostSSAMIR;
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 04:00:17 +0000