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-rw-r--r--backend/unittests/Target/RISCVRegisterAllocationTest.cpp32
-rw-r--r--backend/unittests/Target/RISCVSSAExitTest.cpp23
2 files changed, 30 insertions, 25 deletions
diff --git a/backend/unittests/Target/RISCVRegisterAllocationTest.cpp b/backend/unittests/Target/RISCVRegisterAllocationTest.cpp
index acd4b3a..6daf58a 100644
--- a/backend/unittests/Target/RISCVRegisterAllocationTest.cpp
+++ b/backend/unittests/Target/RISCVRegisterAllocationTest.cpp
@@ -52,10 +52,6 @@ private:
int Failures = 0;
};
-[[nodiscard]] constexpr rcc::Opcode targetOpcode(rcc::riscv::InstructionOpcode Value) noexcept {
- return rcc::Opcode::fromValue(static_cast<std::uint32_t>(Value));
-}
-
[[nodiscard]] constexpr rcc::RegisterClassID
registerClass(rcc::riscv::RegisterClass Value) noexcept {
return rcc::RegisterClassID::fromValue(static_cast<std::uint32_t>(Value));
@@ -108,7 +104,8 @@ buildAddImmediate(rcc::MachineFunction &Function, const rcc::TargetDescription &
rcc::MachineIRBuilder Builder(Function, Target);
if (auto Result = Builder.setInsertPoint(Block); !Result)
return std::unexpected(Result.error());
- auto Pending = Builder.buildInstr(targetOpcode(rcc::riscv::InstructionOpcode::ADDI));
+ auto Pending =
+ Builder.buildInstr(rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::ADDI));
if (!Pending)
return std::unexpected(Pending.error());
if (auto Result = Pending->addDef(Destination); !Result)
@@ -128,7 +125,8 @@ buildAddImmediate(rcc::MachineFunction &Function, const rcc::TargetDescription &
rcc::MachineIRBuilder Builder(Function, Target);
if (auto Result = Builder.setInsertPoint(Block); !Result)
return std::unexpected(Result.error());
- auto Pending = Builder.buildInstr(targetOpcode(rcc::riscv::InstructionOpcode::ADD));
+ auto Pending =
+ Builder.buildInstr(rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::ADD));
if (!Pending)
return std::unexpected(Pending.error());
if (auto Result = Pending->addDef(Destination); !Result)
@@ -198,7 +196,7 @@ enum class AllocatorKind : std::uint8_t {
Block = Block->next()) {
for (const rcc::MachineInstr *Instruction = Block->firstInstruction(); Instruction != nullptr;
Instruction = Instruction->next()) {
- Count += Instruction->opcode() == targetOpcode(Value) ? 1U : 0U;
+ Count += Instruction->opcode() == rcc::riscv::instructionOpcode(Value) ? 1U : 0U;
}
}
return Count;
@@ -277,12 +275,18 @@ void testTargetHooks(TestContext &Context, const rcc::TargetDescription &Target)
Info.emitSpill(Builder, physical(rcc::riscv::PhysicalRegisterID::F11_D),
registerClass(rcc::riscv::RegisterClass::FPR64), *Slot, rcc::LaneMask::all());
Context.expect(GPRReload && GPRSpill && F32Reload && F32Spill && F64Reload && F64Spill &&
- (*GPRReload)->opcode() == targetOpcode(rcc::riscv::InstructionOpcode::LD) &&
- (*GPRSpill)->opcode() == targetOpcode(rcc::riscv::InstructionOpcode::SD) &&
- (*F32Reload)->opcode() == targetOpcode(rcc::riscv::InstructionOpcode::FLW) &&
- (*F32Spill)->opcode() == targetOpcode(rcc::riscv::InstructionOpcode::FSW) &&
- (*F64Reload)->opcode() == targetOpcode(rcc::riscv::InstructionOpcode::FLD) &&
- (*F64Spill)->opcode() == targetOpcode(rcc::riscv::InstructionOpcode::FSD),
+ (*GPRReload)->opcode() ==
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::LD) &&
+ (*GPRSpill)->opcode() ==
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::SD) &&
+ (*F32Reload)->opcode() ==
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::FLW) &&
+ (*F32Spill)->opcode() ==
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::FSW) &&
+ (*F64Reload)->opcode() ==
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::FLD) &&
+ (*F64Spill)->opcode() ==
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::FSD),
"RV64GC hooks must select width- and bank-correct stack instructions");
if (GPRReload && F32Reload && F64Reload) {
Context.expect(
@@ -321,7 +325,7 @@ void testRematerialization(TestContext &Context, const rcc::TargetDescription &T
auto Materialized = Info.rematerialize(Builder, **Definition, *Child, *Original, Target);
Context.expect(Accepted && *Accepted && Materialized &&
(*Materialized)->opcode() ==
- targetOpcode(rcc::riscv::InstructionOpcode::ADDI) &&
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::ADDI) &&
(*Materialized)->operandAt(0)->registerValue() == *Child &&
(*Materialized)->operandAt(1)->registerValue() ==
physical(rcc::riscv::PhysicalRegisterID::X0),
diff --git a/backend/unittests/Target/RISCVSSAExitTest.cpp b/backend/unittests/Target/RISCVSSAExitTest.cpp
index ec98bd1..54a5911 100644
--- a/backend/unittests/Target/RISCVSSAExitTest.cpp
+++ b/backend/unittests/Target/RISCVSSAExitTest.cpp
@@ -46,10 +46,6 @@ private:
int Failures = 0;
};
-[[nodiscard]] rcc::Opcode targetOpcode(rcc::riscv::InstructionOpcode Opcode) {
- return rcc::Opcode::fromValue(static_cast<std::uint32_t>(Opcode));
-}
-
[[nodiscard]] rcc::RegisterBankID bank(rcc::riscv::RegisterBank Bank) {
return rcc::RegisterBankID::fromValue(static_cast<std::uint32_t>(Bank));
}
@@ -91,7 +87,8 @@ buildAddImmediate(rcc::MachineFunction &Function, const rcc::TargetDescription &
auto Point = Builder.setInsertPoint(Block);
if (!Point)
return std::unexpected(Point.error());
- auto Pending = Builder.buildInstr(targetOpcode(rcc::riscv::InstructionOpcode::ADDI));
+ auto Pending =
+ Builder.buildInstr(rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::ADDI));
if (!Pending)
return std::unexpected(Pending.error());
auto Def = Pending->addDef(Destination);
@@ -114,7 +111,8 @@ buildBranchEqual(rcc::MachineFunction &Function, const rcc::TargetDescription &T
auto Point = Builder.setInsertPoint(Block);
if (!Point)
return std::unexpected(Point.error());
- auto Pending = Builder.buildInstr(targetOpcode(rcc::riscv::InstructionOpcode::BEQ));
+ auto Pending =
+ Builder.buildInstr(rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::BEQ));
if (!Pending)
return std::unexpected(Pending.error());
auto LeftUse = Pending->addUse(Left);
@@ -208,7 +206,8 @@ void testBehaviorAndCopyLegality(TestContext &Context, const rcc::TargetDescript
rcc::MachineInstr *Jump = (*First)->lastInstruction();
const auto X0 = rcc::riscv::physicalRegister(rcc::riscv::PhysicalRegisterID::X0);
Context.expect(Jump != nullptr &&
- Jump->opcode() == targetOpcode(rcc::riscv::InstructionOpcode::JAL) &&
+ Jump->opcode() ==
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::JAL) &&
Jump->operandAt(0)->registerValue() == rcc::Register::fromPhysical(*X0) &&
blockOperand(*Jump, 1) != nullptr && blockOperand(*Jump, 1)->Block == *Second,
"RV64GC unconditional branches must use JAL with x0 as the link destination");
@@ -280,7 +279,8 @@ void testCompressedConditionalBranchBehavior(TestContext &Context,
Context.expect(false, "compressed conditional branch insertion point must be established");
return;
}
- auto Pending = Builder.buildInstr(targetOpcode(rcc::riscv::InstructionOpcode::C_BEQZ));
+ auto Pending =
+ Builder.buildInstr(rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::C_BEQZ));
if (!X8 || !Pending || !Pending->addUse(rcc::Register::fromPhysical(*X8)) ||
!Pending->addBasicBlock(**BranchTarget)) {
Context.expect(false, "compressed conditional branch construction must succeed");
@@ -370,7 +370,8 @@ void testRV64GCCriticalEdge(TestContext &Context, const rcc::TargetDescription &
return;
rcc::MachineInstr *Conditional = (*From)->lastInstruction();
Context.expect(Conditional != nullptr &&
- Conditional->opcode() == targetOpcode(rcc::riscv::InstructionOpcode::BEQ) &&
+ Conditional->opcode() ==
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::BEQ) &&
blockOperand(*Conditional, 2) != nullptr &&
blockOperand(*Conditional, 2)->Block == Edge,
"RV64GC BEQ must be redirected to the critical-edge block");
@@ -380,13 +381,13 @@ void testRV64GCCriticalEdge(TestContext &Context, const rcc::TargetDescription &
Context.expect(OtherInstructions.size() == 3 &&
OtherInstructions[1]->opcode() == rcc::opcode(rcc::GenericOpcode::COPY) &&
OtherInstructions[2]->opcode() ==
- targetOpcode(rcc::riscv::InstructionOpcode::JAL) &&
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::JAL) &&
blockOperand(*OtherInstructions[2], 1)->Block == *Merge,
"RV64GC must materialize an unrelated fallthrough before edge-block insertion");
Context.expect(EdgeInstructions.size() == 2 &&
EdgeInstructions[0]->opcode() == rcc::opcode(rcc::GenericOpcode::COPY) &&
EdgeInstructions[1]->opcode() ==
- targetOpcode(rcc::riscv::InstructionOpcode::JAL) &&
+ rcc::riscv::instructionOpcode(rcc::riscv::InstructionOpcode::JAL) &&
EdgeInstructions[1]->operandAt(0)->registerValue() == Zero &&
blockOperand(*EdgeInstructions[1], 1)->Block == *Merge,
"RV64GC edge block must transfer the PHI value and jump to the merge");
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 13:30:14 +0000