diff options
Diffstat (limited to 'backend')
28 files changed, 5272 insertions, 4103 deletions
diff --git a/backend/include/rcc/CodeGen/GlobalISel/GIMatchTableExecutor.h b/backend/include/rcc/CodeGen/GlobalISel/GIMatchTableExecutor.h new file mode 100644 index 0000000..807cb4a --- /dev/null +++ b/backend/include/rcc/CodeGen/GlobalISel/GIMatchTableExecutor.h @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-3.0-or-later + +#ifndef RCC_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H +#define RCC_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H + +#include "rcc/CodeGen/MachineIRTypes.h" +#include "rcc/Support/Error.h" + +#include <cstdint> +#include <span> +#include <string_view> + +namespace rcc { + +class MachineFunction; +class MachineInstr; +class TargetDescription; + +enum class GIMatchTypeKind : std::uint8_t { + Any, + Scalar, + Pointer, +}; + +enum class GIMatchTableOpcode : std::uint8_t { + CheckOpcode, + CheckOperandType, + CheckOperandBank, + CheckOperandClass, + MutateOpcode, + AppendImmediate, + Complete, +}; + +struct GIMatchTableInstruction final { + GIMatchTableOpcode Opcode = GIMatchTableOpcode::Complete; + std::uint16_t OperandIndex = 0; + std::uint32_t Value = 0; + std::uint32_t Auxiliary = 0; + std::int64_t Immediate = 0; +}; + +struct GIMatchTableRule final { + std::string_view Name; + std::uint32_t Priority = 0; + std::uint32_t FirstInstruction = 0; + std::uint32_t InstructionCount = 0; +}; + +struct GIMatchTable final { + std::span<const GIMatchTableInstruction> Instructions; + std::span<const GIMatchTableRule> Rules; +}; + +class GIMatchTableExecutor { +public: + [[nodiscard]] Expected<bool> match(const GIMatchTable &Table, const MachineInstr &Instruction, + const MachineFunction &Function, + const TargetDescription &Target) const; + + // A false result means that no table rule matched. The executor completes all + // predicates before applying the selected rule to MachineIR. + [[nodiscard]] Expected<bool> select(const GIMatchTable &Table, MachineInstr &Instruction, + MachineFunction &Function, + const TargetDescription &Target) const; +}; + +} // namespace rcc + +#endif // RCC_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H diff --git a/backend/include/rcc/CodeGen/GlobalISel/InstructionSelector.h b/backend/include/rcc/CodeGen/GlobalISel/InstructionSelector.h index 4bea4e7..36fca8d 100644 --- a/backend/include/rcc/CodeGen/GlobalISel/InstructionSelector.h +++ b/backend/include/rcc/CodeGen/GlobalISel/InstructionSelector.h @@ -3,7 +3,7 @@ #ifndef RCC_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H #define RCC_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H -#include "rcc/CodeGen/MachineIRTypes.h" +#include "rcc/CodeGen/GlobalISel/GIMatchTableExecutor.h" #include "rcc/Support/Error.h" namespace rcc { @@ -12,7 +12,7 @@ class MachineFunction; class MachineInstr; class TargetDescription; -class InstructionSelector { +class InstructionSelector : public GIMatchTableExecutor { public: virtual ~InstructionSelector() = default; diff --git a/backend/include/rcc/TableGen/Record.h b/backend/include/rcc/TableGen/Record.h index 50ac4c9..94308c7 100644 --- a/backend/include/rcc/TableGen/Record.h +++ b/backend/include/rcc/TableGen/Record.h @@ -205,6 +205,43 @@ struct SourceInstruction final { TextRange Range; }; +struct SourceSelectionTypePredicate final { + std::string Kind; + std::uint32_t Bits = 0; + TextRange Range; +}; + +struct SourceSelectionOperandTypePredicate final { + std::uint32_t OperandIndex = 0; + SourceSelectionTypePredicate Type; + TextRange Range; +}; + +struct SourceSelectionOperandBankPredicate final { + std::uint32_t OperandIndex = 0; + std::string BankSymbol; + TextRange Range; +}; + +struct SourceSelectionOperandClassPredicate final { + std::uint32_t OperandIndex = 0; + std::string ClassSymbol; + TextRange Range; +}; + +struct SourceSelectionRule final { + std::string Symbol; + std::uint32_t Priority = 0; + std::string MatchOpcodeSymbol; + std::optional<SourceSelectionTypePredicate> ResultType; + std::vector<SourceSelectionOperandTypePredicate> OperandTypes; + std::vector<SourceSelectionOperandBankPredicate> OperandBanks; + std::vector<SourceSelectionOperandClassPredicate> OperandClasses; + std::string ResultOpcodeSymbol; + std::vector<std::int64_t> AppendedImmediates; + TextRange Range; +}; + struct DescriptionAST final { SourceTarget Target; std::vector<SourceRegisterUnit> RegisterUnits; @@ -220,6 +257,7 @@ struct DescriptionAST final { std::vector<SourceEncodingCategory> EncodingCategories; std::vector<SourceAssemblyFormat> AssemblyFormats; std::vector<SourceInstruction> Instructions; + std::vector<SourceSelectionRule> SelectionRules; }; [[nodiscard]] std::string lowerASCII(std::string_view Value); diff --git a/backend/lib/CodeGen/GlobalISel/CMakeLists.txt b/backend/lib/CodeGen/GlobalISel/CMakeLists.txt index 8fc50d2..5e3c33f 100644 --- a/backend/lib/CodeGen/GlobalISel/CMakeLists.txt +++ b/backend/lib/CodeGen/GlobalISel/CMakeLists.txt @@ -4,6 +4,7 @@ set( RCCBackendGlobalISelSources CSEInfo.cpp CSEMIRBuilder.cpp + GIMatchTableExecutor.cpp GISelChangeObserver.cpp GISelValueTracking.cpp InstructionSelect.cpp @@ -18,6 +19,7 @@ set( RCCBackendGlobalISelHeaders "${RCC_BACKEND_SOURCE_DIR}/include/rcc/CodeGen/GlobalISel/CSEInfo.h" "${RCC_BACKEND_SOURCE_DIR}/include/rcc/CodeGen/GlobalISel/CSEMIRBuilder.h" + "${RCC_BACKEND_SOURCE_DIR}/include/rcc/CodeGen/GlobalISel/GIMatchTableExecutor.h" "${RCC_BACKEND_SOURCE_DIR}/include/rcc/CodeGen/GlobalISel/GISelChangeObserver.h" "${RCC_BACKEND_SOURCE_DIR}/include/rcc/CodeGen/GlobalISel/GISelValueTracking.h" "${RCC_BACKEND_SOURCE_DIR}/include/rcc/CodeGen/GlobalISel/GISelWorkList.h" @@ -37,6 +39,7 @@ target_sources(RCCBackendCodeGen PRIVATE ${RCCBackendGlobalISelSources}) rcc_backend_register_format_files( "${CMAKE_CURRENT_SOURCE_DIR}/CSEInfo.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/CSEMIRBuilder.cpp" + "${CMAKE_CURRENT_SOURCE_DIR}/GIMatchTableExecutor.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/GISelChangeObserver.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/GISelValueTracking.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/InstructionSelect.cpp" @@ -51,6 +54,7 @@ rcc_backend_register_format_files( rcc_backend_register_tidy_files( "${CMAKE_CURRENT_SOURCE_DIR}/CSEInfo.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/CSEMIRBuilder.cpp" + "${CMAKE_CURRENT_SOURCE_DIR}/GIMatchTableExecutor.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/GISelChangeObserver.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/GISelValueTracking.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/InstructionSelect.cpp" diff --git a/backend/lib/CodeGen/GlobalISel/GIMatchTableExecutor.cpp b/backend/lib/CodeGen/GlobalISel/GIMatchTableExecutor.cpp new file mode 100644 index 0000000..a195d11 --- /dev/null +++ b/backend/lib/CodeGen/GlobalISel/GIMatchTableExecutor.cpp @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-3.0-or-later + +#include "rcc/CodeGen/GlobalISel/GIMatchTableExecutor.h" + +#include "rcc/CodeGen/LowLevelType.h" +#include "rcc/CodeGen/MachineFunction.h" +#include "rcc/CodeGen/MachineInstr.h" +#include "rcc/CodeGen/MachineOperand.h" +#include "rcc/CodeGen/MachineRegisterInfo.h" +#include "rcc/CodeGen/TargetDescription.h" + +#include <cstddef> +#include <optional> +#include <vector> + +namespace rcc { +namespace { + +[[nodiscard]] Expected<std::optional<LowLevelType>> operandType(const MachineInstr &Instruction, + const MachineFunction &Function, + std::size_t OperandIndex) { + const MachineOperand *Operand = Instruction.operandAt(OperandIndex); + const Register *Reg = Operand == nullptr ? nullptr : Operand->getIf<Register>(); + if (Reg == nullptr || !Reg->isVirtual()) + return std::optional<LowLevelType>{}; + auto Info = Function.registerInfo().virtualRegisterInfo(*Reg); + if (!Info) + return std::unexpected(Info.error()); + return Info->get().Type; +} + +[[nodiscard]] Expected<bool> matchesType(const MachineInstr &Instruction, + const MachineFunction &Function, + const GIMatchTableInstruction &Step) { + auto Type = operandType(Instruction, Function, Step.OperandIndex); + if (!Type) + return std::unexpected(Type.error()); + if (!*Type) + return false; + + const auto Kind = static_cast<GIMatchTypeKind>(Step.Auxiliary); + switch (Kind) { + case GIMatchTypeKind::Any: + return Step.Value == 0 || (*Type)->scalarBitWidth() == Step.Value; + case GIMatchTypeKind::Scalar: + return (*Type)->isCategoryNeutralScalar() && (*Type)->scalarBitWidth() == Step.Value; + case GIMatchTypeKind::Pointer: + return (*Type)->isPointer() && (*Type)->scalarBitWidth() == Step.Value; + } + return makeUnexpected(ErrorCode::VerificationError, + "generated match table has an invalid type predicate"); +} + +[[nodiscard]] Expected<bool> matchesBank(const MachineInstr &Instruction, + const MachineFunction &Function, + const GIMatchTableInstruction &Step) { + const MachineOperand *Operand = Instruction.operandAt(Step.OperandIndex); + const Register *Reg = Operand == nullptr ? nullptr : Operand->getIf<Register>(); + if (Reg == nullptr || !Reg->isVirtual()) + return false; + auto Info = Function.registerInfo().virtualRegisterInfo(*Reg); + if (!Info) + return std::unexpected(Info.error()); + const VirtualRegisterInfo &RegisterInfo = Info->get(); + if (!RegisterInfo.Bank) + return false; + return RegisterInfo.Bank->value() == Step.Value; +} + +[[nodiscard]] Expected<bool> matchesClass(const MachineInstr &Instruction, + const MachineFunction &Function, + const GIMatchTableInstruction &Step) { + const MachineOperand *Operand = Instruction.operandAt(Step.OperandIndex); + const Register *Reg = Operand == nullptr ? nullptr : Operand->getIf<Register>(); + if (Reg == nullptr || !Reg->isVirtual()) + return false; + auto Info = Function.registerInfo().virtualRegisterInfo(*Reg); + if (!Info) + return std::unexpected(Info.error()); + const VirtualRegisterInfo &RegisterInfo = Info->get(); + if (!RegisterInfo.RegClass) + return false; + return RegisterInfo.RegClass->value() == Step.Value; +} + +struct MatchedRule final { + Opcode ResultOpcode; + std::vector<std::int64_t> AppendedImmediates; +}; + +[[nodiscard]] Expected<std::optional<MatchedRule>> matchRule(const GIMatchTable &Table, + const GIMatchTableRule &Rule, + const MachineInstr &Instruction, + const MachineFunction &Function) { + const std::size_t First = Rule.FirstInstruction; + const std::size_t Count = Rule.InstructionCount; + if (First > Table.Instructions.size() || Count > Table.Instructions.size() - First) { + return makeUnexpected(ErrorCode::VerificationError, + "generated match table rule has an invalid instruction range"); + } + + MatchedRule Result; + bool HasResultOpcode = false; + bool Applying = false; + bool Complete = false; + for (std::size_t Index = First; Index < First + Count; ++Index) { + const GIMatchTableInstruction &Step = Table.Instructions[Index]; + switch (Step.Opcode) { + case GIMatchTableOpcode::CheckOpcode: + if (Applying) + return makeUnexpected(ErrorCode::VerificationError, + "generated match table performs a predicate after rendering"); + if (Instruction.opcode().value() != Step.Value) + return std::optional<MatchedRule>{}; + break; + case GIMatchTableOpcode::CheckOperandType: { + if (Applying) + return makeUnexpected(ErrorCode::VerificationError, + "generated match table performs a predicate after rendering"); + auto Matched = matchesType(Instruction, Function, Step); + if (!Matched) + return std::unexpected(Matched.error()); + if (!*Matched) + return std::optional<MatchedRule>{}; + break; + } + case GIMatchTableOpcode::CheckOperandBank: { + if (Applying) + return makeUnexpected(ErrorCode::VerificationError, + "generated match table performs a predicate after rendering"); + auto Matched = matchesBank(Instruction, Function, Step); + if (!Matched) + return std::unexpected(Matched.error()); + if (!*Matched) + return std::optional<MatchedRule>{}; + break; + } + case GIMatchTableOpcode::CheckOperandClass: { + if (Applying) + return makeUnexpected(ErrorCode::VerificationError, + "generated match table performs a predicate after rendering"); + auto Matched = matchesClass(Instruction, Function, Step); + if (!Matched) + return std::unexpected(Matched.error()); + if (!*Matched) + return std::optional<MatchedRule>{}; + break; + } + case GIMatchTableOpcode::MutateOpcode: + if (Complete || HasResultOpcode || Step.Value == 0) + return makeUnexpected(ErrorCode::VerificationError, + "generated match table has an invalid opcode mutation"); + Applying = true; + Result.ResultOpcode = Opcode::fromValue(Step.Value); + HasResultOpcode = true; + break; + case GIMatchTableOpcode::AppendImmediate: + if (Complete) + return makeUnexpected(ErrorCode::VerificationError, + "generated match table renders after completion"); + Applying = true; + Result.AppendedImmediates.push_back(Step.Immediate); + break; + case GIMatchTableOpcode::Complete: + if (Complete || !HasResultOpcode || Index + 1 != First + Count) + return makeUnexpected(ErrorCode::VerificationError, + "generated match table has an invalid completion action"); + Complete = true; + break; + } + } + + if (!Complete || !HasResultOpcode) + return makeUnexpected(ErrorCode::VerificationError, + "generated match table rule does not complete rendering"); + return std::optional<MatchedRule>(std::move(Result)); +} + +[[nodiscard]] Expected<void> applyRule(const MatchedRule &Rule, MachineInstr &Instruction, + const TargetDescription &Target) { + const InstructionDescriptor *Descriptor = Target.instructionDescriptor(Rule.ResultOpcode); + if (Descriptor == nullptr) + return makeUnexpected(ErrorCode::VerificationError, + "generated match table selects an unknown instruction opcode"); + if (!Descriptor->Variadic && + Descriptor->Operands.size() != Instruction.operandCount() + Rule.AppendedImmediates.size()) { + return makeUnexpected(ErrorCode::VerificationError, + "generated match table result has an incompatible operand count"); + } + + const Opcode OriginalOpcode = Instruction.opcode(); + auto SetOpcode = Instruction.setOpcode(Rule.ResultOpcode); + if (!SetOpcode) + return std::unexpected(SetOpcode.error()); + const std::size_t OriginalOperandCount = Instruction.operandCount(); + for (const std::int64_t Immediate : Rule.AppendedImmediates) { + auto Added = Instruction.addOperand(MachineOperand::immediate(Immediate)); + if (Added) + continue; + while (Instruction.operandCount() > OriginalOperandCount) { + auto Removed = Instruction.eraseOperand(Instruction.operandCount() - 1U); + if (!Removed) + return std::unexpected(Removed.error()); + } + auto Restored = Instruction.setOpcode(OriginalOpcode); + if (!Restored) + return std::unexpected(Restored.error()); + return std::unexpected(Added.error()); + } + return {}; +} + +} // namespace + +Expected<bool> GIMatchTableExecutor::match(const GIMatchTable &Table, + const MachineInstr &Instruction, + const MachineFunction &Function, + const TargetDescription &Target) const { + for (const GIMatchTableRule &Rule : Table.Rules) { + auto Match = matchRule(Table, Rule, Instruction, Function); + if (!Match) + return std::unexpected(Match.error()); + if (!*Match) + continue; + if (Target.instructionDescriptor((*Match)->ResultOpcode) == nullptr) { + return makeUnexpected(ErrorCode::VerificationError, + "generated match table selects an unknown instruction opcode"); + } + return true; + } + return false; +} + +Expected<bool> GIMatchTableExecutor::select(const GIMatchTable &Table, MachineInstr &Instruction, + MachineFunction &Function, + const TargetDescription &Target) const { + for (const GIMatchTableRule &Rule : Table.Rules) { + auto Match = matchRule(Table, Rule, Instruction, Function); + if (!Match) + return std::unexpected(Match.error()); + if (!*Match) + continue; + auto Applied = applyRule(**Match, Instruction, Target); + if (!Applied) + return std::unexpected(Applied.error()); + return true; + } + return false; +} + +} // namespace rcc diff --git a/backend/lib/TableGen/Parser.cpp b/backend/lib/TableGen/Parser.cpp index 2d7116d..65687da 100644 --- a/backend/lib/TableGen/Parser.cpp +++ b/backend/lib/TableGen/Parser.cpp @@ -40,7 +40,7 @@ public: {"schema", "target", "register_units", "registers", "register_banks", "register_classes", "register_masks", "mir_operand_flags", "named_operands", "immediate_predicates", "scheduling_classes", "encoding_categories", - "assembly_formats", "calling_conventions", "instructions"}, + "assembly_formats", "calling_conventions", "instructions", "selection_rules"}, "target description root")) { return std::nullopt; } @@ -80,6 +80,7 @@ public: requiredNode(*Root, "calling_conventions", "target description root"); const yaml::Node *InstructionsNode = requiredNode(*Root, "instructions", "target description root"); + const yaml::Node *SelectionRulesNode = optionalNode(*Root, "selection_rules"); if (UnitsNode == nullptr || RegistersNode == nullptr || BanksNode == nullptr || ClassesNode == nullptr || MasksNode == nullptr || NamedOperandsNode == nullptr || ImmediatePredicatesNode == nullptr || SchedulingClassesNode == nullptr || @@ -98,7 +99,9 @@ public: !parseEncodingCategories(*EncodingCategoriesNode, Result.EncodingCategories) || !parseAssemblyFormats(*AssemblyFormatsNode, Result.AssemblyFormats) || !parseCallingConventions(*CallingConventionsNode, Result.CallingConventions) || - !parseInstructions(*InstructionsNode, Result.Instructions)) { + !parseInstructions(*InstructionsNode, Result.Instructions) || + (SelectionRulesNode != nullptr && + !parseSelectionRules(*SelectionRulesNode, Result.SelectionRules))) { return std::nullopt; } return Result; @@ -1025,6 +1028,195 @@ private: return Result; } + [[nodiscard]] std::optional<SourceSelectionTypePredicate> + parseSelectionTypePredicate(const yaml::Node &Node, std::string_view Context) { + if (!requireMapping(&Node, Context)) + return std::nullopt; + if (!checkKeys(Node, {"kind", "bits"}, Context)) + return std::nullopt; + const auto Kind = requiredScalar(Node, "kind", Context); + const yaml::Node *BitsNode = requiredNode(Node, "bits", Context); + if (!Kind || BitsNode == nullptr) + return std::nullopt; + const auto Bits = unsignedInteger32(*BitsNode, std::string(Context) + " bits"); + if (!Bits) + return std::nullopt; + return SourceSelectionTypePredicate{ + .Kind = *Kind, + .Bits = *Bits, + .Range = Node.range(), + }; + } + + [[nodiscard]] bool + parseSelectionOperandTypes(const yaml::Node &Node, + std::vector<SourceSelectionOperandTypePredicate> &Result) { + if (!requireSequence(&Node, "selection operand type predicates")) + return false; + for (const yaml::NodeID ElementID : Node.sequence()) { + const yaml::Node *Element = Input.node(ElementID); + if (!requireMapping(Element, "selection operand type predicate") || + !checkKeys(*Element, {"index", "kind", "bits"}, "selection operand type predicate")) { + return false; + } + const yaml::Node *IndexNode = + requiredNode(*Element, "index", "selection operand type predicate"); + const auto Kind = requiredScalar(*Element, "kind", "selection operand type predicate"); + const yaml::Node *BitsNode = + requiredNode(*Element, "bits", "selection operand type predicate"); + if (IndexNode == nullptr || !Kind || BitsNode == nullptr) + return false; + const auto Index = unsignedInteger32(*IndexNode, "selection operand type index"); + const auto Bits = unsignedInteger32(*BitsNode, "selection operand type bits"); + if (!Index || !Bits) + return false; + Result.push_back({ + .OperandIndex = *Index, + .Type = {.Kind = *Kind, .Bits = *Bits, .Range = Element->range()}, + .Range = Element->range(), + }); + } + return true; + } + + [[nodiscard]] bool + parseSelectionOperandBanks(const yaml::Node &Node, + std::vector<SourceSelectionOperandBankPredicate> &Result) { + if (!requireSequence(&Node, "selection operand bank predicates")) + return false; + for (const yaml::NodeID ElementID : Node.sequence()) { + const yaml::Node *Element = Input.node(ElementID); + if (!requireMapping(Element, "selection operand bank predicate") || + !checkKeys(*Element, {"index", "bank"}, "selection operand bank predicate")) { + return false; + } + const yaml::Node *IndexNode = + requiredNode(*Element, "index", "selection operand bank predicate"); + const auto Bank = requiredScalar(*Element, "bank", "selection operand bank predicate"); + if (IndexNode == nullptr || !Bank) + return false; + const auto Index = unsignedInteger32(*IndexNode, "selection operand bank index"); + if (!Index) + return false; + Result.push_back({ + .OperandIndex = *Index, + .BankSymbol = *Bank, + .Range = Element->range(), + }); + } + return true; + } + + [[nodiscard]] bool + parseSelectionOperandClasses(const yaml::Node &Node, + std::vector<SourceSelectionOperandClassPredicate> &Result) { + if (!requireSequence(&Node, "selection operand class predicates")) + return false; + for (const yaml::NodeID ElementID : Node.sequence()) { + const yaml::Node *Element = Input.node(ElementID); + if (!requireMapping(Element, "selection operand class predicate") || + !checkKeys(*Element, {"index", "class"}, "selection operand class predicate")) { + return false; + } + const yaml::Node *IndexNode = + requiredNode(*Element, "index", "selection operand class predicate"); + const auto Class = requiredScalar(*Element, "class", "selection operand class predicate"); + if (IndexNode == nullptr || !Class) + return false; + const auto Index = unsignedInteger32(*IndexNode, "selection operand class index"); + if (!Index) + return false; + Result.push_back({ + .OperandIndex = *Index, + .ClassSymbol = *Class, + .Range = Element->range(), + }); + } + return true; + } + + [[nodiscard]] bool parseSelectionRuleMatch(const yaml::Node &Node, SourceSelectionRule &Result) { + if (!requireMapping(&Node, "selection rule match") || + !checkKeys(Node, + {"opcode", "result_type", "operand_types", "operand_banks", "operand_classes"}, + "selection rule match")) { + return false; + } + const auto Opcode = requiredScalar(Node, "opcode", "selection rule match"); + if (!Opcode) + return false; + Result.MatchOpcodeSymbol = *Opcode; + if (const yaml::Node *ResultType = optionalNode(Node, "result_type")) { + auto Parsed = parseSelectionTypePredicate(*ResultType, "selection result type predicate"); + if (!Parsed) + return false; + Result.ResultType = std::move(*Parsed); + } + if (const yaml::Node *OperandTypes = optionalNode(Node, "operand_types")) { + if (!parseSelectionOperandTypes(*OperandTypes, Result.OperandTypes)) + return false; + } + if (const yaml::Node *OperandBanks = optionalNode(Node, "operand_banks")) { + if (!parseSelectionOperandBanks(*OperandBanks, Result.OperandBanks)) + return false; + } + if (const yaml::Node *OperandClasses = optionalNode(Node, "operand_classes")) { + if (!parseSelectionOperandClasses(*OperandClasses, Result.OperandClasses)) + return false; + } + return true; + } + + [[nodiscard]] bool parseSelectionRuleApply(const yaml::Node &Node, SourceSelectionRule &Result) { + if (!requireMapping(&Node, "selection rule apply") || + !checkKeys(Node, {"opcode", "append_immediates"}, "selection rule apply")) { + return false; + } + const auto Opcode = requiredScalar(Node, "opcode", "selection rule apply"); + if (!Opcode) + return false; + Result.ResultOpcodeSymbol = *Opcode; + if (const yaml::Node *Immediates = optionalNode(Node, "append_immediates")) { + auto Values = signedIntegerSequence(*Immediates, "selection rule appended immediates"); + if (!Values) + return false; + Result.AppendedImmediates = std::move(*Values); + } + return true; + } + + [[nodiscard]] bool parseSelectionRules(const yaml::Node &Node, + std::vector<SourceSelectionRule> &Result) { + if (!requireSequence(&Node, "selection_rules")) + return false; + for (const yaml::NodeID ElementID : Node.sequence()) { + const yaml::Node *Element = Input.node(ElementID); + if (!requireMapping(Element, "selection rule") || + !checkKeys(*Element, {"id", "priority", "match", "apply"}, "selection rule")) { + return false; + } + const auto Symbol = requiredScalar(*Element, "id", "selection rule"); + const yaml::Node *PriorityNode = requiredNode(*Element, "priority", "selection rule"); + const yaml::Node *MatchNode = requiredNode(*Element, "match", "selection rule"); + const yaml::Node *ApplyNode = requiredNode(*Element, "apply", "selection rule"); + if (!Symbol || PriorityNode == nullptr || MatchNode == nullptr || ApplyNode == nullptr) + return false; + const auto Priority = unsignedInteger32(*PriorityNode, "selection rule priority"); + if (!Priority) + return false; + SourceSelectionRule Rule; + Rule.Symbol = *Symbol; + Rule.Priority = *Priority; + Rule.Range = Element->range(); + if (!parseSelectionRuleMatch(*MatchNode, Rule) || + !parseSelectionRuleApply(*ApplyNode, Rule)) { + return false; + } + Result.push_back(std::move(Rule)); + } + return true; + } + [[nodiscard]] bool parseInstructions(const yaml::Node &Node, std::vector<SourceInstruction> &Result) { if (!requireSequence(&Node, "instructions")) diff --git a/backend/lib/Target/RISCV/CMakeLists.txt b/backend/lib/Target/RISCV/CMakeLists.txt index c4dbdf7..bd6bf3d 100644 --- a/backend/lib/Target/RISCV/CMakeLists.txt +++ b/backend/lib/Target/RISCV/CMakeLists.txt @@ -1,6 +1,25 @@ # SPDX-License-Identifier: GPL-3.0-or-later -set(RCCBackendRISCVDescription "${CMAKE_CURRENT_SOURCE_DIR}/RISCV.rccdesc") +set( + RCCBackendRISCVDescriptionSources + "${CMAKE_CURRENT_SOURCE_DIR}/RISCV.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVRegisterInfo.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVCallingConv.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfoBase.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfoI.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfoM.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfoA.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfoF.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfoD.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfoC.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfoZb.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVInstrInfoPseudo.rccdesc" + "${CMAKE_CURRENT_SOURCE_DIR}/RISCVGISel.rccdesc" +) +set(RCCBackendRISCVTableGenArguments) +foreach(RCCBackendRISCVDescriptionSource IN LISTS RCCBackendRISCVDescriptionSources) + list(APPEND RCCBackendRISCVTableGenArguments --input "${RCCBackendRISCVDescriptionSource}") +endforeach() set( RCCBackendRISCVGeneratedRegisterHeader "${RCC_BACKEND_BINARY_DIR}/generated/include/rcc/Target/RISCV/RISCVRegisters.h" @@ -13,19 +32,25 @@ set( RCCBackendRISCVGeneratedTables "${RCC_BACKEND_BINARY_DIR}/generated/lib/Target/RISCV/RISCVGenTargetDescription.inc" ) +set( + RCCBackendRISCVGeneratedGlobalISel + "${RCC_BACKEND_BINARY_DIR}/generated/lib/Target/RISCV/RISCVGenGlobalISel.inc" +) add_custom_command( OUTPUT "${RCCBackendRISCVGeneratedRegisterHeader}" "${RCCBackendRISCVGeneratedInstructionHeader}" "${RCCBackendRISCVGeneratedTables}" + "${RCCBackendRISCVGeneratedGlobalISel}" COMMAND "$<TARGET_FILE:RCCBackendTableGenTool>" - --input "${RCCBackendRISCVDescription}" + ${RCCBackendRISCVTableGenArguments} --register-header "${RCCBackendRISCVGeneratedRegisterHeader}" --instruction-header "${RCCBackendRISCVGeneratedInstructionHeader}" --tables "${RCCBackendRISCVGeneratedTables}" - DEPENDS RCCBackendTableGenTool "${RCCBackendRISCVDescription}" + --global-isel "${RCCBackendRISCVGeneratedGlobalISel}" + DEPENDS RCCBackendTableGenTool ${RCCBackendRISCVDescriptionSources} COMMENT "Generating RCC RV64GC target tables" VERBATIM ) @@ -36,12 +61,14 @@ add_custom_target( "${RCCBackendRISCVGeneratedRegisterHeader}" "${RCCBackendRISCVGeneratedInstructionHeader}" "${RCCBackendRISCVGeneratedTables}" + "${RCCBackendRISCVGeneratedGlobalISel}" ) set_source_files_properties( "${RCCBackendRISCVGeneratedRegisterHeader}" "${RCCBackendRISCVGeneratedInstructionHeader}" "${RCCBackendRISCVGeneratedTables}" + "${RCCBackendRISCVGeneratedGlobalISel}" PROPERTIES GENERATED TRUE HEADER_FILE_ONLY TRUE ) @@ -74,6 +101,7 @@ add_library( "${RCCBackendRISCVGeneratedRegisterHeader}" "${RCCBackendRISCVGeneratedInstructionHeader}" "${RCCBackendRISCVGeneratedTables}" + "${RCCBackendRISCVGeneratedGlobalISel}" ) add_library(RCCBackend::RISCV ALIAS RCCBackendRISCV) add_dependencies(RCCBackendRISCV RCCBackendRISCVGeneratedTablesTarget) diff --git a/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index 62c10af..68574a3 100644 --- a/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -5,7 +5,6 @@ #include "RISCVRegisterBankInfo.h" #include "rcc/CodeGen/GenericOpcodes.h" #include "rcc/CodeGen/GlobalISel/InstructionSelector.h" -#include "rcc/CodeGen/GlobalISel/LegalizerInfo.h" #include "rcc/CodeGen/LowLevelType.h" #include "rcc/CodeGen/MachineBasicBlock.h" #include "rcc/CodeGen/MachineFunction.h" @@ -33,6 +32,10 @@ namespace rcc::riscv { namespace { +#define GET_GLOBALISEL_MATCH_TABLE +#include "RISCVGenGlobalISel.inc" +#undef GET_GLOBALISEL_MATCH_TABLE + [[nodiscard]] std::optional<LowLevelType> registerType(const MachineFunction &Function, const MachineOperand &Operand) { const Register *Reg = Operand.getIf<Register>(); @@ -72,12 +75,6 @@ operandType(const MachineFunction &Function, const MachineInstr &Instruction, st Type.scalarBitWidth() <= 64; } -[[nodiscard]] bool isScalarGPRType(LowLevelType Type) noexcept { - return (Type.isCategoryNeutralScalar() && Type.scalarBitWidth() != 0 && - Type.scalarBitWidth() <= 64) || - (Type.isPointer() && Type.scalarBitWidth() == 64); -} - [[nodiscard]] constexpr RegisterBankID fprBank() noexcept { return RegisterBankID::fromValue(static_cast<std::uint32_t>(RegisterBank::FPR)); } @@ -183,39 +180,23 @@ public: [[nodiscard]] Expected<void> canSelect(const MachineInstr &Instruction, const MachineFunction &Function, const TargetDescription &Target) const override { - if (Instruction.opcode() == instructionOpcode(InstructionOpcode::G_SLLW) || - Instruction.opcode() == instructionOpcode(InstructionOpcode::G_SRAW) || - Instruction.opcode() == instructionOpcode(InstructionOpcode::G_SRLW) || - Instruction.opcode() == instructionOpcode(InstructionOpcode::G_DIVW) || - Instruction.opcode() == instructionOpcode(InstructionOpcode::G_DIVUW) || - Instruction.opcode() == instructionOpcode(InstructionOpcode::G_REMUW)) { - const std::optional<LowLevelType> Type = resultType(Function, Instruction); - const std::optional<LowLevelType> Left = operandType(Function, Instruction, 1); - const std::optional<LowLevelType> Right = operandType(Function, Instruction, 2); - return Type && Left && Right && isScalarGPRType(*Type) && Type->scalarBitWidth() == 64 && - *Left == *Type && *Right == *Type - ? Expected<void>{} - : makeUnexpected(ErrorCode::Unsupported, - "RISC-V word shift pseudo requires three 64-bit GPR operands"); - } - if (!isGenericOpcode(Instruction.opcode())) + auto Generated = + GIMatchTableExecutor::match(generatedGlobalISelMatchTable(), Instruction, Function, Target); + if (!Generated) + return std::unexpected(Generated.error()); + if (*Generated) return {}; + if (!isGenericOpcode(Instruction.opcode())) { + const InstructionDescriptor *Descriptor = Target.instructionDescriptor(Instruction.opcode()); + if (Descriptor != nullptr && !Descriptor->Flags.has(InstructionFlag::Generic)) + return {}; + return makeUnexpected(ErrorCode::Unsupported, + "RISC-V instruction selector has no generated rule for target pseudo"); + } const GenericOpcode Generic = static_cast<GenericOpcode>(Instruction.opcode().value()); const std::optional<LowLevelType> Type = resultType(Function, Instruction); const auto Integer = [Type] { return Type && isSupportedIntegerType(*Type); }; const auto Float = [Type] { return Type && isSupportedFloatingScalar(*Type); }; - auto Classification = Subtarget.getLegalizerInfo()->getDecision(Instruction, Function, Target); - if (!Classification) - return std::unexpected(Classification.error()); - if (Classification->Action != LegalizationAction::Legal && - Classification->Action != LegalizationAction::Custom) { - std::string Message = "RISC-V selector cannot select opcode '" + - std::string(getGenericOpcodeName(Generic)) + "'"; - if (Type) - Message += " with result type '" + Type->toString() + "'"; - Message += ": the legalization rule explicitly marks this combination unsupported"; - return makeUnexpected(ErrorCode::Unsupported, std::move(Message)); - } switch (Generic) { case GenericOpcode::G_ADD: case GenericOpcode::G_SUB: @@ -343,21 +324,15 @@ public: [[nodiscard]] Expected<void> select(MachineInstr &Instruction, MachineFunction &Function, const TargetDescription &Target) const override { + auto Generated = GIMatchTableExecutor::select(generatedGlobalISelMatchTable(), Instruction, + Function, Target); + if (!Generated) + return std::unexpected(Generated.error()); + if (*Generated) + return {}; auto Match = canSelect(Instruction, Function, Target); if (!Match) return std::unexpected(Match.error()); - if (Instruction.opcode() == instructionOpcode(InstructionOpcode::G_SLLW)) - return Instruction.setOpcode(instructionOpcode(InstructionOpcode::SLLW)); - if (Instruction.opcode() == instructionOpcode(InstructionOpcode::G_SRAW)) - return Instruction.setOpcode(instructionOpcode(InstructionOpcode::SRAW)); - if (Instruction.opcode() == instructionOpcode(InstructionOpcode::G_SRLW)) - return Instruction.setOpcode(instructionOpcode(InstructionOpcode::SRLW)); - if (Instruction.opcode() == instructionOpcode(InstructionOpcode::G_DIVW)) - return Instruction.setOpcode(instructionOpcode(InstructionOpcode::DIVW)); - if (Instruction.opcode() == instructionOpcode(InstructionOpcode::G_DIVUW)) - return Instruction.setOpcode(instructionOpcode(InstructionOpcode::DIVUW)); - if (Instruction.opcode() == instructionOpcode(InstructionOpcode::G_REMUW)) - return Instruction.setOpcode(instructionOpcode(InstructionOpcode::REMUW)); const GenericOpcode Generic = static_cast<GenericOpcode>(Instruction.opcode().value()); const std::optional<LowLevelType> Type = resultType(Function, Instruction); diff --git a/backend/lib/Target/RISCV/RISCV.rccdesc b/backend/lib/Target/RISCV/RISCV.rccdesc index 832e8c1..7623afd 100644 --- a/backend/lib/Target/RISCV/RISCV.rccdesc +++ b/backend/lib/Target/RISCV/RISCV.rccdesc @@ -9,4032 +9,3 @@ target: abi: lp64d data_layout: e-m:e-p:64:64-i64:64-i128:128-n32:64-S128 features: [i, m, a, f, d, c, zicsr, zifencei] - -register_units: - - { id: 1, symbol: U_X0, name: x0.unit } - - { id: 2, symbol: U_X1, name: x1.unit } - - { id: 3, symbol: U_X2, name: x2.unit } - - { id: 4, symbol: U_X3, name: x3.unit } - - { id: 5, symbol: U_X4, name: x4.unit } - - { id: 6, symbol: U_X5, name: x5.unit } - - { id: 7, symbol: U_X6, name: x6.unit } - - { id: 8, symbol: U_X7, name: x7.unit } - - { id: 9, symbol: U_X8, name: x8.unit } - - { id: 10, symbol: U_X9, name: x9.unit } - - { id: 11, symbol: U_X10, name: x10.unit } - - { id: 12, symbol: U_X11, name: x11.unit } - - { id: 13, symbol: U_X12, name: x12.unit } - - { id: 14, symbol: U_X13, name: x13.unit } - - { id: 15, symbol: U_X14, name: x14.unit } - - { id: 16, symbol: U_X15, name: x15.unit } - - { id: 17, symbol: U_X16, name: x16.unit } - - { id: 18, symbol: U_X17, name: x17.unit } - - { id: 19, symbol: U_X18, name: x18.unit } - - { id: 20, symbol: U_X19, name: x19.unit } - - { id: 21, symbol: U_X20, name: x20.unit } - - { id: 22, symbol: U_X21, name: x21.unit } - - { id: 23, symbol: U_X22, name: x22.unit } - - { id: 24, symbol: U_X23, name: x23.unit } - - { id: 25, symbol: U_X24, name: x24.unit } - - { id: 26, symbol: U_X25, name: x25.unit } - - { id: 27, symbol: U_X26, name: x26.unit } - - { id: 28, symbol: U_X27, name: x27.unit } - - { id: 29, symbol: U_X28, name: x28.unit } - - { id: 30, symbol: U_X29, name: x29.unit } - - { id: 31, symbol: U_X30, name: x30.unit } - - { id: 32, symbol: U_X31, name: x31.unit } - - { id: 33, symbol: U_F0, name: f0.unit } - - { id: 34, symbol: U_F1, name: f1.unit } - - { id: 35, symbol: U_F2, name: f2.unit } - - { id: 36, symbol: U_F3, name: f3.unit } - - { id: 37, symbol: U_F4, name: f4.unit } - - { id: 38, symbol: U_F5, name: f5.unit } - - { id: 39, symbol: U_F6, name: f6.unit } - - { id: 40, symbol: U_F7, name: f7.unit } - - { id: 41, symbol: U_F8, name: f8.unit } - - { id: 42, symbol: U_F9, name: f9.unit } - - { id: 43, symbol: U_F10, name: f10.unit } - - { id: 44, symbol: U_F11, name: f11.unit } - - { id: 45, symbol: U_F12, name: f12.unit } - - { id: 46, symbol: U_F13, name: f13.unit } - - { id: 47, symbol: U_F14, name: f14.unit } - - { id: 48, symbol: U_F15, name: f15.unit } - - { id: 49, symbol: U_F16, name: f16.unit } - - { id: 50, symbol: U_F17, name: f17.unit } - - { id: 51, symbol: U_F18, name: f18.unit } - - { id: 52, symbol: U_F19, name: f19.unit } - - { id: 53, symbol: U_F20, name: f20.unit } - - { id: 54, symbol: U_F21, name: f21.unit } - - { id: 55, symbol: U_F22, name: f22.unit } - - { id: 56, symbol: U_F23, name: f23.unit } - - { id: 57, symbol: U_F24, name: f24.unit } - - { id: 58, symbol: U_F25, name: f25.unit } - - { id: 59, symbol: U_F26, name: f26.unit } - - { id: 60, symbol: U_F27, name: f27.unit } - - { id: 61, symbol: U_F28, name: f28.unit } - - { id: 62, symbol: U_F29, name: f29.unit } - - { id: 63, symbol: U_F30, name: f30.unit } - - { id: 64, symbol: U_F31, name: f31.unit } - - { id: 65, symbol: U_FFLAGS, name: fflags.unit } - - { id: 66, symbol: U_FRM, name: frm.unit } - - { id: 67, symbol: U_V0, name: v0.unit } - - { id: 68, symbol: U_V1, name: v1.unit } - - { id: 69, symbol: U_V2, name: v2.unit } - - { id: 70, symbol: U_V3, name: v3.unit } - - { id: 71, symbol: U_V4, name: v4.unit } - - { id: 72, symbol: U_V5, name: v5.unit } - - { id: 73, symbol: U_V6, name: v6.unit } - - { id: 74, symbol: U_V7, name: v7.unit } - - { id: 75, symbol: U_V8, name: v8.unit } - - { id: 76, symbol: U_V9, name: v9.unit } - - { id: 77, symbol: U_V10, name: v10.unit } - - { id: 78, symbol: U_V11, name: v11.unit } - - { id: 79, symbol: U_V12, name: v12.unit } - - { id: 80, symbol: U_V13, name: v13.unit } - - { id: 81, symbol: U_V14, name: v14.unit } - - { id: 82, symbol: U_V15, name: v15.unit } - - { id: 83, symbol: U_V16, name: v16.unit } - - { id: 84, symbol: U_V17, name: v17.unit } - - { id: 85, symbol: U_V18, name: v18.unit } - - { id: 86, symbol: U_V19, name: v19.unit } - - { id: 87, symbol: U_V20, name: v20.unit } - - { id: 88, symbol: U_V21, name: v21.unit } - - { id: 89, symbol: U_V22, name: v22.unit } - - { id: 90, symbol: U_V23, name: v23.unit } - - { id: 91, symbol: U_V24, name: v24.unit } - - { id: 92, symbol: U_V25, name: v25.unit } - - { id: 93, symbol: U_V26, name: v26.unit } - - { id: 94, symbol: U_V27, name: v27.unit } - - { id: 95, symbol: U_V28, name: v28.unit } - - { id: 96, symbol: U_V29, name: v29.unit } - - { id: 97, symbol: U_V30, name: v30.unit } - - { id: 98, symbol: U_V31, name: v31.unit } - -registers: - - { id: 1, symbol: X0, name: x0, encoding: 0, dwarf_register: 0, units: [{ unit: U_X0, lanes: 1 }], constant: true, reserved: true, aliases: [zero] } - - { id: 2, symbol: X1, name: x1, encoding: 1, dwarf_register: 1, units: [{ unit: U_X1, lanes: 1 }], aliases: [ra] } - - { id: 3, symbol: X2, name: x2, encoding: 2, dwarf_register: 2, units: [{ unit: U_X2, lanes: 1 }], reserved: true, aliases: [sp] } - - { id: 4, symbol: X3, name: x3, encoding: 3, dwarf_register: 3, units: [{ unit: U_X3, lanes: 1 }], reserved: true, aliases: [gp] } - - { id: 5, symbol: X4, name: x4, encoding: 4, dwarf_register: 4, units: [{ unit: U_X4, lanes: 1 }], reserved: true, aliases: [tp] } - - { id: 6, symbol: X5, name: x5, encoding: 5, dwarf_register: 5, units: [{ unit: U_X5, lanes: 1 }], aliases: [t0] } - - { id: 7, symbol: X6, name: x6, encoding: 6, dwarf_register: 6, units: [{ unit: U_X6, lanes: 1 }], aliases: [t1] } - - { id: 8, symbol: X7, name: x7, encoding: 7, dwarf_register: 7, units: [{ unit: U_X7, lanes: 1 }], aliases: [t2] } - - { id: 9, symbol: X8, name: x8, encoding: 8, dwarf_register: 8, units: [{ unit: U_X8, lanes: 1 }], aliases: [s0, fp] } - - { id: 10, symbol: X9, name: x9, encoding: 9, dwarf_register: 9, units: [{ unit: U_X9, lanes: 1 }], aliases: [s1] } - - { id: 11, symbol: X10, name: x10, encoding: 10, dwarf_register: 10, units: [{ unit: U_X10, lanes: 1 }], aliases: [a0] } - - { id: 12, symbol: X11, name: x11, encoding: 11, dwarf_register: 11, units: [{ unit: U_X11, lanes: 1 }], aliases: [a1] } - - { id: 13, symbol: X12, name: x12, encoding: 12, dwarf_register: 12, units: [{ unit: U_X12, lanes: 1 }], aliases: [a2] } - - { id: 14, symbol: X13, name: x13, encoding: 13, dwarf_register: 13, units: [{ unit: U_X13, lanes: 1 }], aliases: [a3] } - - { id: 15, symbol: X14, name: x14, encoding: 14, dwarf_register: 14, units: [{ unit: U_X14, lanes: 1 }], aliases: [a4] } - - { id: 16, symbol: X15, name: x15, encoding: 15, dwarf_register: 15, units: [{ unit: U_X15, lanes: 1 }], aliases: [a5] } - - { id: 17, symbol: X16, name: x16, encoding: 16, dwarf_register: 16, units: [{ unit: U_X16, lanes: 1 }], aliases: [a6] } - - { id: 18, symbol: X17, name: x17, encoding: 17, dwarf_register: 17, units: [{ unit: U_X17, lanes: 1 }], aliases: [a7] } - - { id: 19, symbol: X18, name: x18, encoding: 18, dwarf_register: 18, units: [{ unit: U_X18, lanes: 1 }], aliases: [s2] } - - { id: 20, symbol: X19, name: x19, encoding: 19, dwarf_register: 19, units: [{ unit: U_X19, lanes: 1 }], aliases: [s3] } - - { id: 21, symbol: X20, name: x20, encoding: 20, dwarf_register: 20, units: [{ unit: U_X20, lanes: 1 }], aliases: [s4] } - - { id: 22, symbol: X21, name: x21, encoding: 21, dwarf_register: 21, units: [{ unit: U_X21, lanes: 1 }], aliases: [s5] } - - { id: 23, symbol: X22, name: x22, encoding: 22, dwarf_register: 22, units: [{ unit: U_X22, lanes: 1 }], aliases: [s6] } - - { id: 24, symbol: X23, name: x23, encoding: 23, dwarf_register: 23, units: [{ unit: U_X23, lanes: 1 }], aliases: [s7] } - - { id: 25, symbol: X24, name: x24, encoding: 24, dwarf_register: 24, units: [{ unit: U_X24, lanes: 1 }], aliases: [s8] } - - { id: 26, symbol: X25, name: x25, encoding: 25, dwarf_register: 25, units: [{ unit: U_X25, lanes: 1 }], aliases: [s9] } - - { id: 27, symbol: X26, name: x26, encoding: 26, dwarf_register: 26, units: [{ unit: U_X26, lanes: 1 }], aliases: [s10] } - - { id: 28, symbol: X27, name: x27, encoding: 27, dwarf_register: 27, units: [{ unit: U_X27, lanes: 1 }], aliases: [s11] } - - { id: 29, symbol: X28, name: x28, encoding: 28, dwarf_register: 28, units: [{ unit: U_X28, lanes: 1 }], aliases: [t3] } - - { id: 30, symbol: X29, name: x29, encoding: 29, dwarf_register: 29, units: [{ unit: U_X29, lanes: 1 }], aliases: [t4] } - - { id: 31, symbol: X30, name: x30, encoding: 30, dwarf_register: 30, units: [{ unit: U_X30, lanes: 1 }], aliases: [t5] } - - { id: 32, symbol: X31, name: x31, encoding: 31, dwarf_register: 31, units: [{ unit: U_X31, lanes: 1 }], aliases: [t6] } - - { id: 33, symbol: F0_D, name: f0_d, encoding: 0, dwarf_register: 32, units: [{ unit: U_F0, lanes: 1 }], aliases: [ft0] } - - { id: 34, symbol: F1_D, name: f1_d, encoding: 1, dwarf_register: 33, units: [{ unit: U_F1, lanes: 1 }], aliases: [ft1] } - - { id: 35, symbol: F2_D, name: f2_d, encoding: 2, dwarf_register: 34, units: [{ unit: U_F2, lanes: 1 }], aliases: [ft2] } - - { id: 36, symbol: F3_D, name: f3_d, encoding: 3, dwarf_register: 35, units: [{ unit: U_F3, lanes: 1 }], aliases: [ft3] } - - { id: 37, symbol: F4_D, name: f4_d, encoding: 4, dwarf_register: 36, units: [{ unit: U_F4, lanes: 1 }], aliases: [ft4] } - - { id: 38, symbol: F5_D, name: f5_d, encoding: 5, dwarf_register: 37, units: [{ unit: U_F5, lanes: 1 }], aliases: [ft5] } - - { id: 39, symbol: F6_D, name: f6_d, encoding: 6, dwarf_register: 38, units: [{ unit: U_F6, lanes: 1 }], aliases: [ft6] } - - { id: 40, symbol: F7_D, name: f7_d, encoding: 7, dwarf_register: 39, units: [{ unit: U_F7, lanes: 1 }], aliases: [ft7] } - - { id: 41, symbol: F8_D, name: f8_d, encoding: 8, dwarf_register: 40, units: [{ unit: U_F8, lanes: 1 }], aliases: [fs0] } - - { id: 42, symbol: F9_D, name: f9_d, encoding: 9, dwarf_register: 41, units: [{ unit: U_F9, lanes: 1 }], aliases: [fs1] } - - { id: 43, symbol: F10_D, name: f10_d, encoding: 10, dwarf_register: 42, units: [{ unit: U_F10, lanes: 1 }], aliases: [fa0] } - - { id: 44, symbol: F11_D, name: f11_d, encoding: 11, dwarf_register: 43, units: [{ unit: U_F11, lanes: 1 }], aliases: [fa1] } - - { id: 45, symbol: F12_D, name: f12_d, encoding: 12, dwarf_register: 44, units: [{ unit: U_F12, lanes: 1 }], aliases: [fa2] } - - { id: 46, symbol: F13_D, name: f13_d, encoding: 13, dwarf_register: 45, units: [{ unit: U_F13, lanes: 1 }], aliases: [fa3] } - - { id: 47, symbol: F14_D, name: f14_d, encoding: 14, dwarf_register: 46, units: [{ unit: U_F14, lanes: 1 }], aliases: [fa4] } - - { id: 48, symbol: F15_D, name: f15_d, encoding: 15, dwarf_register: 47, units: [{ unit: U_F15, lanes: 1 }], aliases: [fa5] } - - { id: 49, symbol: F16_D, name: f16_d, encoding: 16, dwarf_register: 48, units: [{ unit: U_F16, lanes: 1 }], aliases: [fa6] } - - { id: 50, symbol: F17_D, name: f17_d, encoding: 17, dwarf_register: 49, units: [{ unit: U_F17, lanes: 1 }], aliases: [fa7] } - - { id: 51, symbol: F18_D, name: f18_d, encoding: 18, dwarf_register: 50, units: [{ unit: U_F18, lanes: 1 }], aliases: [fs2] } - - { id: 52, symbol: F19_D, name: f19_d, encoding: 19, dwarf_register: 51, units: [{ unit: U_F19, lanes: 1 }], aliases: [fs3] } - - { id: 53, symbol: F20_D, name: f20_d, encoding: 20, dwarf_register: 52, units: [{ unit: U_F20, lanes: 1 }], aliases: [fs4] } - - { id: 54, symbol: F21_D, name: f21_d, encoding: 21, dwarf_register: 53, units: [{ unit: U_F21, lanes: 1 }], aliases: [fs5] } - - { id: 55, symbol: F22_D, name: f22_d, encoding: 22, dwarf_register: 54, units: [{ unit: U_F22, lanes: 1 }], aliases: [fs6] } - - { id: 56, symbol: F23_D, name: f23_d, encoding: 23, dwarf_register: 55, units: [{ unit: U_F23, lanes: 1 }], aliases: [fs7] } - - { id: 57, symbol: F24_D, name: f24_d, encoding: 24, dwarf_register: 56, units: [{ unit: U_F24, lanes: 1 }], aliases: [fs8] } - - { id: 58, symbol: F25_D, name: f25_d, encoding: 25, dwarf_register: 57, units: [{ unit: U_F25, lanes: 1 }], aliases: [fs9] } - - { id: 59, symbol: F26_D, name: f26_d, encoding: 26, dwarf_register: 58, units: [{ unit: U_F26, lanes: 1 }], aliases: [fs10] } - - { id: 60, symbol: F27_D, name: f27_d, encoding: 27, dwarf_register: 59, units: [{ unit: U_F27, lanes: 1 }], aliases: [fs11] } - - { id: 61, symbol: F28_D, name: f28_d, encoding: 28, dwarf_register: 60, units: [{ unit: U_F28, lanes: 1 }], aliases: [ft8] } - - { id: 62, symbol: F29_D, name: f29_d, encoding: 29, dwarf_register: 61, units: [{ unit: U_F29, lanes: 1 }], aliases: [ft9] } - - { id: 63, symbol: F30_D, name: f30_d, encoding: 30, dwarf_register: 62, units: [{ unit: U_F30, lanes: 1 }], aliases: [ft10] } - - { id: 64, symbol: F31_D, name: f31_d, encoding: 31, dwarf_register: 63, units: [{ unit: U_F31, lanes: 1 }], aliases: [ft11] } - - { id: 65, symbol: F0_F, name: f0_f, encoding: 0, dwarf_register: 32, units: [{ unit: U_F0, lanes: 1 }] } - - { id: 66, symbol: F1_F, name: f1_f, encoding: 1, dwarf_register: 33, units: [{ unit: U_F1, lanes: 1 }] } - - { id: 67, symbol: F2_F, name: f2_f, encoding: 2, dwarf_register: 34, units: [{ unit: U_F2, lanes: 1 }] } - - { id: 68, symbol: F3_F, name: f3_f, encoding: 3, dwarf_register: 35, units: [{ unit: U_F3, lanes: 1 }] } - - { id: 69, symbol: F4_F, name: f4_f, encoding: 4, dwarf_register: 36, units: [{ unit: U_F4, lanes: 1 }] } - - { id: 70, symbol: F5_F, name: f5_f, encoding: 5, dwarf_register: 37, units: [{ unit: U_F5, lanes: 1 }] } - - { id: 71, symbol: F6_F, name: f6_f, encoding: 6, dwarf_register: 38, units: [{ unit: U_F6, lanes: 1 }] } - - { id: 72, symbol: F7_F, name: f7_f, encoding: 7, dwarf_register: 39, units: [{ unit: U_F7, lanes: 1 }] } - - { id: 73, symbol: F8_F, name: f8_f, encoding: 8, dwarf_register: 40, units: [{ unit: U_F8, lanes: 1 }] } - - { id: 74, symbol: F9_F, name: f9_f, encoding: 9, dwarf_register: 41, units: [{ unit: U_F9, lanes: 1 }] } - - { id: 75, symbol: F10_F, name: f10_f, encoding: 10, dwarf_register: 42, units: [{ unit: U_F10, lanes: 1 }] } - - { id: 76, symbol: F11_F, name: f11_f, encoding: 11, dwarf_register: 43, units: [{ unit: U_F11, lanes: 1 }] } - - { id: 77, symbol: F12_F, name: f12_f, encoding: 12, dwarf_register: 44, units: [{ unit: U_F12, lanes: 1 }] } - - { id: 78, symbol: F13_F, name: f13_f, encoding: 13, dwarf_register: 45, units: [{ unit: U_F13, lanes: 1 }] } - - { id: 79, symbol: F14_F, name: f14_f, encoding: 14, dwarf_register: 46, units: [{ unit: U_F14, lanes: 1 }] } - - { id: 80, symbol: F15_F, name: f15_f, encoding: 15, dwarf_register: 47, units: [{ unit: U_F15, lanes: 1 }] } - - { id: 81, symbol: F16_F, name: f16_f, encoding: 16, dwarf_register: 48, units: [{ unit: U_F16, lanes: 1 }] } - - { id: 82, symbol: F17_F, name: f17_f, encoding: 17, dwarf_register: 49, units: [{ unit: U_F17, lanes: 1 }] } - - { id: 83, symbol: F18_F, name: f18_f, encoding: 18, dwarf_register: 50, units: [{ unit: U_F18, lanes: 1 }] } - - { id: 84, symbol: F19_F, name: f19_f, encoding: 19, dwarf_register: 51, units: [{ unit: U_F19, lanes: 1 }] } - - { id: 85, symbol: F20_F, name: f20_f, encoding: 20, dwarf_register: 52, units: [{ unit: U_F20, lanes: 1 }] } - - { id: 86, symbol: F21_F, name: f21_f, encoding: 21, dwarf_register: 53, units: [{ unit: U_F21, lanes: 1 }] } - - { id: 87, symbol: F22_F, name: f22_f, encoding: 22, dwarf_register: 54, units: [{ unit: U_F22, lanes: 1 }] } - - { id: 88, symbol: F23_F, name: f23_f, encoding: 23, dwarf_register: 55, units: [{ unit: U_F23, lanes: 1 }] } - - { id: 89, symbol: F24_F, name: f24_f, encoding: 24, dwarf_register: 56, units: [{ unit: U_F24, lanes: 1 }] } - - { id: 90, symbol: F25_F, name: f25_f, encoding: 25, dwarf_register: 57, units: [{ unit: U_F25, lanes: 1 }] } - - { id: 91, symbol: F26_F, name: f26_f, encoding: 26, dwarf_register: 58, units: [{ unit: U_F26, lanes: 1 }] } - - { id: 92, symbol: F27_F, name: f27_f, encoding: 27, dwarf_register: 59, units: [{ unit: U_F27, lanes: 1 }] } - - { id: 93, symbol: F28_F, name: f28_f, encoding: 28, dwarf_register: 60, units: [{ unit: U_F28, lanes: 1 }] } - - { id: 94, symbol: F29_F, name: f29_f, encoding: 29, dwarf_register: 61, units: [{ unit: U_F29, lanes: 1 }] } - - { id: 95, symbol: F30_F, name: f30_f, encoding: 30, dwarf_register: 62, units: [{ unit: U_F30, lanes: 1 }] } - - { id: 96, symbol: F31_F, name: f31_f, encoding: 31, dwarf_register: 63, units: [{ unit: U_F31, lanes: 1 }] } - - { id: 97, symbol: FFLAGS, name: fflags, encoding: 0, dwarf_register: 65, units: [{ unit: U_FFLAGS, lanes: 1 }], artificial: true, reserved: true } - - { id: 98, symbol: FRM, name: frm, encoding: 0, dwarf_register: 66, units: [{ unit: U_FRM, lanes: 1 }], artificial: true, reserved: true } - - { id: 99, symbol: V0, name: v0, encoding: 0, dwarf_register: 96, units: [{ unit: U_V0, lanes: 1 }] } - - { id: 100, symbol: V1, name: v1, encoding: 1, dwarf_register: 97, units: [{ unit: U_V1, lanes: 1 }] } - - { id: 101, symbol: V2, name: v2, encoding: 2, dwarf_register: 98, units: [{ unit: U_V2, lanes: 1 }] } - - { id: 102, symbol: V3, name: v3, encoding: 3, dwarf_register: 99, units: [{ unit: U_V3, lanes: 1 }] } - - { id: 103, symbol: V4, name: v4, encoding: 4, dwarf_register: 100, units: [{ unit: U_V4, lanes: 1 }] } - - { id: 104, symbol: V5, name: v5, encoding: 5, dwarf_register: 101, units: [{ unit: U_V5, lanes: 1 }] } - - { id: 105, symbol: V6, name: v6, encoding: 6, dwarf_register: 102, units: [{ unit: U_V6, lanes: 1 }] } - - { id: 106, symbol: V7, name: v7, encoding: 7, dwarf_register: 103, units: [{ unit: U_V7, lanes: 1 }] } - - { id: 107, symbol: V8, name: v8, encoding: 8, dwarf_register: 104, units: [{ unit: U_V8, lanes: 1 }] } - - { id: 108, symbol: V9, name: v9, encoding: 9, dwarf_register: 105, units: [{ unit: U_V9, lanes: 1 }] } - - { id: 109, symbol: V10, name: v10, encoding: 10, dwarf_register: 106, units: [{ unit: U_V10, lanes: 1 }] } - - { id: 110, symbol: V11, name: v11, encoding: 11, dwarf_register: 107, units: [{ unit: U_V11, lanes: 1 }] } - - { id: 111, symbol: V12, name: v12, encoding: 12, dwarf_register: 108, units: [{ unit: U_V12, lanes: 1 }] } - - { id: 112, symbol: V13, name: v13, encoding: 13, dwarf_register: 109, units: [{ unit: U_V13, lanes: 1 }] } - - { id: 113, symbol: V14, name: v14, encoding: 14, dwarf_register: 110, units: [{ unit: U_V14, lanes: 1 }] } - - { id: 114, symbol: V15, name: v15, encoding: 15, dwarf_register: 111, units: [{ unit: U_V15, lanes: 1 }] } - - { id: 115, symbol: V16, name: v16, encoding: 16, dwarf_register: 112, units: [{ unit: U_V16, lanes: 1 }] } - - { id: 116, symbol: V17, name: v17, encoding: 17, dwarf_register: 113, units: [{ unit: U_V17, lanes: 1 }] } - - { id: 117, symbol: V18, name: v18, encoding: 18, dwarf_register: 114, units: [{ unit: U_V18, lanes: 1 }] } - - { id: 118, symbol: V19, name: v19, encoding: 19, dwarf_register: 115, units: [{ unit: U_V19, lanes: 1 }] } - - { id: 119, symbol: V20, name: v20, encoding: 20, dwarf_register: 116, units: [{ unit: U_V20, lanes: 1 }] } - - { id: 120, symbol: V21, name: v21, encoding: 21, dwarf_register: 117, units: [{ unit: U_V21, lanes: 1 }] } - - { id: 121, symbol: V22, name: v22, encoding: 22, dwarf_register: 118, units: [{ unit: U_V22, lanes: 1 }] } - - { id: 122, symbol: V23, name: v23, encoding: 23, dwarf_register: 119, units: [{ unit: U_V23, lanes: 1 }] } - - { id: 123, symbol: V24, name: v24, encoding: 24, dwarf_register: 120, units: [{ unit: U_V24, lanes: 1 }] } - - { id: 124, symbol: V25, name: v25, encoding: 25, dwarf_register: 121, units: [{ unit: U_V25, lanes: 1 }] } - - { id: 125, symbol: V26, name: v26, encoding: 26, dwarf_register: 122, units: [{ unit: U_V26, lanes: 1 }] } - - { id: 126, symbol: V27, name: v27, encoding: 27, dwarf_register: 123, units: [{ unit: U_V27, lanes: 1 }] } - - { id: 127, symbol: V28, name: v28, encoding: 28, dwarf_register: 124, units: [{ unit: U_V28, lanes: 1 }] } - - { id: 128, symbol: V29, name: v29, encoding: 29, dwarf_register: 125, units: [{ unit: U_V29, lanes: 1 }] } - - { id: 129, symbol: V30, name: v30, encoding: 30, dwarf_register: 126, units: [{ unit: U_V30, lanes: 1 }] } - - { id: 130, symbol: V31, name: v31, encoding: 31, dwarf_register: 127, units: [{ unit: U_V31, lanes: 1 }] } - -register_banks: - - { id: 1, symbol: GPR, name: GPRB, maximum_size_bits: 64 } - - { id: 2, symbol: FPR, name: FPRB, maximum_size_bits: 64 } - - { id: 3, symbol: CSR, name: CSRB, maximum_size_bits: 32 } - - { id: 4, symbol: VR, name: VRB, maximum_size_bits: 512 } - -register_classes: - - - id: 1 - symbol: GPR - name: GPR - bank: GPR - size_bits: 64 - spill_size_bits: 64 - spill_alignment_bits: 64 - lanes: 1 - registers: [X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] - allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] - - - id: 2 - symbol: GPRC - name: GPRC - bank: GPR - size_bits: 64 - spill_size_bits: 64 - spill_alignment_bits: 64 - lanes: 1 - registers: [X8, X9, X10, X11, X12, X13, X14, X15] - allocation_order: [X10, X11, X12, X13, X14, X15, X8, X9] - - - id: 3 - symbol: FPR64 - name: FPR64 - bank: FPR - size_bits: 64 - spill_size_bits: 64 - spill_alignment_bits: 64 - lanes: 1 - registers: [F0_D, F1_D, F2_D, F3_D, F4_D, F5_D, F6_D, F7_D, F8_D, F9_D, F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D, F28_D, F29_D, F30_D, F31_D] - allocation_order: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D, F0_D, F1_D, F2_D, F3_D, F4_D, F5_D, F6_D, F7_D, F28_D, F29_D, F30_D, F31_D, F8_D, F9_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D] - - - id: 4 - symbol: FPR64C - name: FPR64C - bank: FPR - size_bits: 64 - spill_size_bits: 64 - spill_alignment_bits: 64 - lanes: 1 - registers: [F8_D, F9_D, F10_D, F11_D, F12_D, F13_D, F14_D, F15_D] - allocation_order: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F8_D, F9_D] - - - id: 5 - symbol: FPR32 - name: FPR32 - bank: FPR - size_bits: 32 - spill_size_bits: 32 - spill_alignment_bits: 32 - lanes: 1 - registers: [F0_F, F1_F, F2_F, F3_F, F4_F, F5_F, F6_F, F7_F, F8_F, F9_F, F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F16_F, F17_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F, F28_F, F29_F, F30_F, F31_F] - allocation_order: [F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F16_F, F17_F, F0_F, F1_F, F2_F, F3_F, F4_F, F5_F, F6_F, F7_F, F28_F, F29_F, F30_F, F31_F, F8_F, F9_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F] - - - id: 6 - symbol: FPR32C - name: FPR32C - bank: FPR - size_bits: 32 - spill_size_bits: 32 - spill_alignment_bits: 32 - lanes: 1 - registers: [F8_F, F9_F, F10_F, F11_F, F12_F, F13_F, F14_F, F15_F] - allocation_order: [F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F8_F, F9_F] - - - id: 7 - symbol: GPR_NX0 - name: GPR_NX0 - bank: GPR - size_bits: 64 - spill_size_bits: 64 - spill_alignment_bits: 64 - lanes: 1 - registers: [X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] - allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] - - - id: 8 - symbol: GPR_NX0_NX2 - name: GPR_NX0_NX2 - bank: GPR - size_bits: 64 - spill_size_bits: 64 - spill_alignment_bits: 64 - lanes: 1 - registers: [X1, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] - allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] - - - id: 9 - symbol: FFLAGS - name: FFLAGS - bank: CSR - size_bits: 32 - spill_size_bits: 32 - spill_alignment_bits: 32 - lanes: 1 - registers: [FFLAGS] - allocation_order: [] - allocatable: false - - - id: 10 - symbol: FRM - name: FRM - bank: CSR - size_bits: 32 - spill_size_bits: 32 - spill_alignment_bits: 32 - lanes: 1 - registers: [FRM] - allocation_order: [] - allocatable: false - - - id: 11 - symbol: VR - name: VR - bank: VR - size_bits: 64 - spill_size_bits: 64 - spill_alignment_bits: 64 - lanes: 1 - registers: [V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31] - allocation_order: [] - allocatable: false - -register_masks: - - - name: CSR_ILP32_LP64 - preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27] - - - name: CSR_ILP32D_LP64D - preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, F8_D, F9_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D, F8_F, F9_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F] - -mir_operand_flags: - direct_mask: 127 - direct: - - { name: riscv-call, value: 1 } - - { name: riscv-pcrel-hi, value: 2 } - - { name: riscv-pcrel-lo, value: 4 } - - { name: riscv-copy-f32, value: 8 } - - { name: riscv-copy-f64, value: 16 } - - { name: riscv-hi, value: 32 } - - { name: riscv-lo, value: 64 } - bitmask: [] - -calling_conventions: - - - id: 2 - symbol: LP64 - name: lp64 - integer_register_class: GPR - floating_register_class: FPR64 - integer_argument_registers: [X10, X11, X12, X13, X14, X15, X16, X17] - floating_argument_registers: [] - integer_return_registers: [X10, X11] - floating_return_registers: [] - preserved_mask: CSR_ILP32_LP64 - stack_alignment_bytes: 16 - stack_argument_alignment_bytes: 16 - shadow_space_bytes: 0 - supports_varargs: true - supports_tail_calls: true - - - id: 1 - symbol: LP64D - name: lp64d - integer_register_class: GPR - floating_register_class: FPR64 - integer_argument_registers: [X10, X11, X12, X13, X14, X15, X16, X17] - floating_argument_registers: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D] - integer_return_registers: [X10, X11] - floating_return_registers: [F10_D, F11_D] - preserved_mask: CSR_ILP32D_LP64D - stack_alignment_bytes: 16 - stack_argument_alignment_bytes: 16 - shadow_space_bytes: 0 - supports_varargs: true - supports_tail_calls: true - -named_operands: - - { id: 1, symbol: RD, name: rd } - - { id: 2, symbol: RS1, name: rs1 } - - { id: 3, symbol: RS2, name: rs2 } - - { id: 4, symbol: IMM, name: imm } - - { id: 5, symbol: TARGET, name: target } - - { id: 6, symbol: CSR, name: csr } - - { id: 7, symbol: ZIMM, name: zimm } - - { id: 8, symbol: PRED, name: pred } - - { id: 9, symbol: SUCC, name: succ } - - { id: 10, symbol: FRD, name: frd } - - { id: 11, symbol: FRS1, name: frs1 } - - { id: 12, symbol: FRS2, name: frs2 } - - { id: 13, symbol: FRS3, name: frs3 } - - { id: 14, symbol: RM, name: rm } - -immediate_predicates: - - { id: 1, symbol: SIMM12, name: simm12, kind: signed, bits: 12 } - - { id: 2, symbol: UIMM20, name: uimm20, kind: unsigned, bits: 20 } - - { id: 3, symbol: UIMM5, name: uimm5, kind: unsigned, bits: 5 } - - { id: 4, symbol: UIMM6, name: uimm6, kind: unsigned, bits: 6 } - - { id: 5, symbol: UIMM12, name: uimm12, kind: unsigned, bits: 12 } - - { id: 6, symbol: UIMM4, name: uimm4, kind: unsigned, bits: 4 } - - { id: 7, symbol: RM, name: rm, kind: unsigned, bits: 3, allowed_values: [0, 1, 2, 3, 4, 7] } - - { id: 8, symbol: C_UIMM10_NZ_A4, name: c-uimm10-nz-a4, kind: unsigned, bits: 10, alignment: 4, nonzero: true } - - { id: 9, symbol: C_UIMM7_A4, name: c-uimm7-a4, kind: unsigned, bits: 7, alignment: 4 } - - { id: 10, symbol: C_UIMM8_A8, name: c-uimm8-a8, kind: unsigned, bits: 8, alignment: 8 } - - { id: 11, symbol: C_UIMM8_A4, name: c-uimm8-a4, kind: unsigned, bits: 8, alignment: 4 } - - { id: 12, symbol: C_UIMM9_A8, name: c-uimm9-a8, kind: unsigned, bits: 9, alignment: 8 } - - { id: 13, symbol: C_SIMM6, name: c-simm6, kind: signed, bits: 6 } - - { id: 14, symbol: C_SIMM6_NZ, name: c-simm6-nz, kind: signed, bits: 6, nonzero: true } - - { id: 15, symbol: C_SIMM9_A2, name: c-simm9-a2, kind: signed, bits: 9, alignment: 2 } - - { id: 16, symbol: C_SIMM12_A2, name: c-simm12-a2, kind: signed, bits: 12, alignment: 2 } - - { id: 17, symbol: C_SIMM10_A16_NZ, name: c-simm10-a16-nz, kind: signed, bits: 10, alignment: 16, nonzero: true } - -scheduling_classes: - - { id: 1, symbol: ALU, name: alu, micro_ops: 1, latency: 1 } - - { id: 2, symbol: LOAD, name: load, micro_ops: 1, latency: 3 } - - { id: 3, symbol: STORE, name: store, micro_ops: 1, latency: 1 } - - { id: 4, symbol: BRANCH, name: branch, micro_ops: 1, latency: 1 } - - { id: 5, symbol: SYSTEM, name: system, micro_ops: 1, latency: 1 } - - { id: 6, symbol: MUL, name: mul, micro_ops: 1, latency: 3 } - - { id: 7, symbol: DIV, name: div, micro_ops: 1, latency: 20 } - - { id: 8, symbol: FENCE, name: fence, micro_ops: 1, latency: 1 } - - { id: 9, symbol: ATOMIC, name: atomic, micro_ops: 1, latency: 4 } - - { id: 10, symbol: FP_ADD, name: fp-add, micro_ops: 1, latency: 4 } - - { id: 11, symbol: FP_MUL, name: fp-mul, micro_ops: 1, latency: 4 } - - { id: 12, symbol: FP_DIV, name: fp-div, micro_ops: 1, latency: 20 } - - { id: 13, symbol: FP_SQRT, name: fp-sqrt, micro_ops: 1, latency: 20 } - - { id: 14, symbol: FP_CONVERT, name: fp-convert, micro_ops: 1, latency: 4 } - - { id: 15, symbol: COMPRESSED, name: compressed, micro_ops: 1, latency: 1 } - -encoding_categories: - - { id: 1, symbol: R, name: r, size_bytes: 4 } - - { id: 2, symbol: I, name: i, size_bytes: 4 } - - { id: 3, symbol: S, name: s, size_bytes: 4 } - - { id: 4, symbol: B, name: b, size_bytes: 4 } - - { id: 5, symbol: U, name: u, size_bytes: 4 } - - { id: 6, symbol: J, name: j, size_bytes: 4 } - - { id: 7, symbol: SYSTEM, name: system, size_bytes: 4 } - - { id: 8, symbol: AMO, name: amo, size_bytes: 4 } - - { id: 9, symbol: R4, name: r4, size_bytes: 4 } - - { id: 10, symbol: C, name: c, size_bytes: 2 } - -assembly_formats: - - { id: 1, symbol: RD_IMM, name: rd-imm } - - { id: 2, symbol: RD_RS1_IMM, name: rd-rs1-imm } - - { id: 3, symbol: RD_RS1_RS2, name: rd-rs1-rs2 } - - { id: 4, symbol: RD_OFFSET_RS1, name: rd-offset-rs1 } - - { id: 5, symbol: RS2_OFFSET_RS1, name: rs2-offset-rs1 } - - { id: 6, symbol: RS1_RS2_TARGET, name: rs1-rs2-target } - - { id: 7, symbol: RD_TARGET, name: rd-target } - - { id: 8, symbol: NONE, name: none } - - { id: 9, symbol: IMM_IMM, name: imm-imm } - - { id: 10, symbol: RD_CSR_RS1, name: rd-csr-rs1 } - - { id: 11, symbol: RD_CSR_IMM, name: rd-csr-imm } - - { id: 12, symbol: RD_PAREN_RS1, name: rd-paren-rs1 } - - { id: 13, symbol: RD_RS2_PAREN_RS1, name: rd-rs2-paren-rs1 } - - { id: 14, symbol: FRD_OFFSET_RS1, name: frd-offset-rs1 } - - { id: 15, symbol: FRS2_OFFSET_RS1, name: frs2-offset-rs1 } - - { id: 16, symbol: FRD_FRS1_FRS2_RM, name: frd-frs1-frs2-rm } - - { id: 17, symbol: FRD_FRS1_FRS2_FRS3_RM, name: frd-frs1-frs2-frs3-rm } - - { id: 18, symbol: FRD_FRS1_RM, name: frd-frs1-rm } - - { id: 19, symbol: FRD_FRS1_FRS2, name: frd-frs1-frs2 } - - { id: 20, symbol: RD_FRS1_RM, name: rd-frs1-rm } - - { id: 21, symbol: RD_FRS1, name: rd-frs1 } - - { id: 22, symbol: RD_FRS1_FRS2, name: rd-frs1-frs2 } - - { id: 23, symbol: FRD_RS1_RM, name: frd-rs1-rm } - - { id: 24, symbol: FRD_RS1, name: frd-rs1 } - - { id: 25, symbol: TARGET, name: target } - - { id: 26, symbol: RS1_TARGET, name: rs1-target } - - { id: 27, symbol: RS1, name: rs1 } - - { id: 28, symbol: RD_RS2, name: rd-rs2 } - - { id: 29, symbol: IMM_SP, name: imm-sp } - - { id: 30, symbol: RD_IMM_SP, name: rd-imm-sp } - - { id: 31, symbol: RD_OFFSET_SP, name: rd-offset-sp } - - { id: 32, symbol: RS2_OFFSET_SP, name: rs2-offset-sp } - - { id: 33, symbol: FRD_OFFSET_SP, name: frd-offset-sp } - - { id: 34, symbol: FRS2_OFFSET_SP, name: frs2-offset-sp } - - { id: 35, symbol: RD_RS1, name: rd-rs1 } - -instructions: - - - id: 1024 - symbol: LUI - name: LUI - assembly_mnemonic: lui - encoding: 5175 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: UIMM20, allowed_target_flags: 32, name: IMM } - num_explicit_defs: 1 - flags: [produces_code, rematerializable] - scheduling_class: ALU - encoding_category: U - assembly_format: RD_IMM - - - id: 1025 - symbol: AUIPC - name: AUIPC - assembly_mnemonic: auipc - encoding: 5143 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate, basic_block, global_symbol, external_symbol, mc_symbol], immediate_predicate: UIMM20, allowed_target_flags: 3, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: U - assembly_format: RD_IMM - - - id: 1026 - symbol: ADDI - name: ADDI - assembly_mnemonic: addi - encoding: 1344531 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 68, name: IMM } - num_explicit_defs: 1 - flags: [produces_code, rematerializable] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1042 - symbol: SRLI - name: SRLI - assembly_mnemonic: srli - encoding: 1365011 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1043 - symbol: SRAI - name: SRAI - assembly_mnemonic: srai - encoding: 1075106835 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1044 - symbol: ADDIW - name: ADDIW - assembly_mnemonic: addiw - encoding: 1344539 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } - num_explicit_defs: 1 - flags: [produces_code, rematerializable] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1045 - symbol: SLLIW - name: SLLIW - assembly_mnemonic: slliw - encoding: 1348635 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: UIMM5, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1046 - symbol: SRLIW - name: SRLIW - assembly_mnemonic: srliw - encoding: 1365019 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: UIMM5, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1047 - symbol: SRAIW - name: SRAIW - assembly_mnemonic: sraiw - encoding: 1075106843 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: UIMM5, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1048 - symbol: SLL - name: SLL - assembly_mnemonic: sll - encoding: 10785843 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1049 - symbol: SLT - name: SLT - assembly_mnemonic: slt - encoding: 10789939 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1050 - symbol: SLTU - name: SLTU - assembly_mnemonic: sltu - encoding: 10794035 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1051 - symbol: XOR - name: XOR - assembly_mnemonic: xor - encoding: 10798131 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1052 - symbol: SRL - name: SRL - assembly_mnemonic: srl - encoding: 10802227 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1053 - symbol: SRA - name: SRA - assembly_mnemonic: sra - encoding: 1084544051 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1054 - symbol: OR - name: OR - assembly_mnemonic: or - encoding: 10806323 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1055 - symbol: AND - name: AND - assembly_mnemonic: and - encoding: 10810419 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1056 - symbol: ADDW - name: ADDW - assembly_mnemonic: addw - encoding: 10781755 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1057 - symbol: SUBW - name: SUBW - assembly_mnemonic: subw - encoding: 1084523579 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1058 - symbol: SLLW - name: SLLW - assembly_mnemonic: sllw - encoding: 10785851 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1059 - symbol: SRLW - name: SRLW - assembly_mnemonic: srlw - encoding: 10802235 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1060 - symbol: SRAW - name: SRAW - assembly_mnemonic: sraw - encoding: 1084544059 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1061 - symbol: LB - name: LB - assembly_mnemonic: lb - encoding: 8684547 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: I - assembly_format: RD_OFFSET_RS1 - - - id: 1062 - symbol: LH - name: LH - assembly_mnemonic: lh - encoding: 8688643 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: I - assembly_format: RD_OFFSET_RS1 - - - id: 1063 - symbol: LW - name: LW - assembly_mnemonic: lw - encoding: 8692739 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: I - assembly_format: RD_OFFSET_RS1 - - - id: 1064 - symbol: LBU - name: LBU - assembly_mnemonic: lbu - encoding: 8700931 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: I - assembly_format: RD_OFFSET_RS1 - - - id: 1065 - symbol: LHU - name: LHU - assembly_mnemonic: lhu - encoding: 8705027 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: I - assembly_format: RD_OFFSET_RS1 - - - id: 1066 - symbol: LWU - name: LWU - assembly_mnemonic: lwu - encoding: 8709123 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: I - assembly_format: RD_OFFSET_RS1 - - - id: 1067 - symbol: SB - name: SB - assembly_mnemonic: sb - encoding: 10781731 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 0 - flags: [may_store, produces_code] - scheduling_class: STORE - encoding_category: S - assembly_format: RS2_OFFSET_RS1 - - - id: 1068 - symbol: SH - name: SH - assembly_mnemonic: sh - encoding: 10785827 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 0 - flags: [may_store, produces_code] - scheduling_class: STORE - encoding_category: S - assembly_format: RS2_OFFSET_RS1 - - - id: 1069 - symbol: SW - name: SW - assembly_mnemonic: sw - encoding: 10789923 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 0 - flags: [may_store, produces_code] - scheduling_class: STORE - encoding_category: S - assembly_format: RS2_OFFSET_RS1 - - - id: 1070 - symbol: BLT - name: BLT - assembly_mnemonic: blt - encoding: 9715811 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [terminator, branch, produces_code] - scheduling_class: BRANCH - encoding_category: B - assembly_format: RS1_RS2_TARGET - - - id: 1071 - symbol: BGE - name: BGE - assembly_mnemonic: bge - encoding: 9719907 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [terminator, branch, produces_code] - scheduling_class: BRANCH - encoding_category: B - assembly_format: RS1_RS2_TARGET - - - id: 1072 - symbol: BLTU - name: BLTU - assembly_mnemonic: bltu - encoding: 9724003 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [terminator, branch, produces_code] - scheduling_class: BRANCH - encoding_category: B - assembly_format: RS1_RS2_TARGET - - - id: 1073 - symbol: BGEU - name: BGEU - assembly_mnemonic: bgeu - encoding: 9728099 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [terminator, branch, produces_code] - scheduling_class: BRANCH - encoding_category: B - assembly_format: RS1_RS2_TARGET - - - id: 1074 - symbol: JALR - name: JALR - assembly_mnemonic: jalr - encoding: 1344615 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate, basic_block, global_symbol, external_symbol, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 4, name: IMM } - num_explicit_defs: 1 - flags: [terminator, branch, indirect_branch, produces_code] - scheduling_class: BRANCH - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1075 - symbol: FENCE - name: FENCE - assembly_mnemonic: fence - encoding: 15 - operands: - - { kinds: [immediate], immediate_predicate: UIMM4, name: PRED } - - { kinds: [immediate], immediate_predicate: UIMM4, name: SUCC } - num_explicit_defs: 0 - flags: [has_side_effects, produces_code] - scheduling_class: FENCE - encoding_category: I - assembly_format: IMM_IMM - - - id: 1076 - symbol: FENCE_I - name: FENCE_I - assembly_mnemonic: fence.i - encoding: 4111 - operands: [] - num_explicit_defs: 0 - flags: [has_side_effects, produces_code] - scheduling_class: FENCE - encoding_category: I - assembly_format: NONE - - - id: 1077 - symbol: CSRRW - name: CSRRW - assembly_mnemonic: csrrw - encoding: 1348723 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [has_side_effects, produces_code] - scheduling_class: SYSTEM - encoding_category: SYSTEM - assembly_format: RD_CSR_RS1 - - - id: 1078 - symbol: CSRRS - name: CSRRS - assembly_mnemonic: csrrs - encoding: 1352819 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [has_side_effects, produces_code] - scheduling_class: SYSTEM - encoding_category: SYSTEM - assembly_format: RD_CSR_RS1 - - - id: 1079 - symbol: CSRRC - name: CSRRC - assembly_mnemonic: csrrc - encoding: 1356915 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - num_explicit_defs: 1 - flags: [has_side_effects, produces_code] - scheduling_class: SYSTEM - encoding_category: SYSTEM - assembly_format: RD_CSR_RS1 - - - id: 1080 - symbol: CSRRWI - name: CSRRWI - assembly_mnemonic: csrrwi - encoding: 1102963 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } - - { kinds: [immediate], immediate_predicate: UIMM5, name: ZIMM } - num_explicit_defs: 1 - flags: [has_side_effects, produces_code] - scheduling_class: SYSTEM - encoding_category: SYSTEM - assembly_format: RD_CSR_IMM - - - id: 1083 - symbol: MUL - name: MUL - assembly_mnemonic: mul - encoding: 44336179 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code, commutable] - scheduling_class: MUL - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1084 - symbol: MULH - name: MULH - assembly_mnemonic: mulh - encoding: 44340275 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code, commutable] - scheduling_class: MUL - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1085 - symbol: MULHSU - name: MULHSU - assembly_mnemonic: mulhsu - encoding: 44344371 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: MUL - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1086 - symbol: MULHU - name: MULHU - assembly_mnemonic: mulhu - encoding: 44348467 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code, commutable] - scheduling_class: MUL - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1087 - symbol: DIV - name: DIV - assembly_mnemonic: div - encoding: 44352563 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: DIV - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1088 - symbol: DIVU - name: DIVU - assembly_mnemonic: divu - encoding: 44356659 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: DIV - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1089 - symbol: REM - name: REM - assembly_mnemonic: rem - encoding: 44360755 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: DIV - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1090 - symbol: REMU - name: REMU - assembly_mnemonic: remu - encoding: 44364851 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: DIV - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1091 - symbol: MULW - name: MULW - assembly_mnemonic: mulw - encoding: 44336187 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code, commutable] - scheduling_class: MUL - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1092 - symbol: DIVW - name: DIVW - assembly_mnemonic: divw - encoding: 44352571 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: DIV - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1093 - symbol: DIVUW - name: DIVUW - assembly_mnemonic: divuw - encoding: 44356667 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: DIV - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1094 - symbol: REMW - name: REMW - assembly_mnemonic: remw - encoding: 44360763 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: DIV - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1095 - symbol: REMUW - name: REMUW - assembly_mnemonic: remuw - encoding: 44364859 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: DIV - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1081 - symbol: CSRRSI - name: CSRRSI - assembly_mnemonic: csrrsi - encoding: 1107059 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } - - { kinds: [immediate], immediate_predicate: UIMM5, name: ZIMM } - num_explicit_defs: 1 - flags: [has_side_effects, produces_code] - scheduling_class: SYSTEM - encoding_category: SYSTEM - assembly_format: RD_CSR_IMM - - - id: 1082 - symbol: CSRRCI - name: CSRRCI - assembly_mnemonic: csrrci - encoding: 1111155 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } - - { kinds: [immediate], immediate_predicate: UIMM5, name: ZIMM } - num_explicit_defs: 1 - flags: [has_side_effects, produces_code] - scheduling_class: SYSTEM - encoding_category: SYSTEM - assembly_format: RD_CSR_IMM - - - id: 1027 - symbol: ADD - name: ADD - assembly_mnemonic: add - encoding: 10781747 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1028 - symbol: SUB - name: SUB - assembly_mnemonic: sub - encoding: 1084523571 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1029 - symbol: LD - name: LD - assembly_mnemonic: ld - encoding: 8696835 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: I - assembly_format: RD_OFFSET_RS1 - - - id: 1030 - symbol: SD - name: SD - assembly_mnemonic: sd - encoding: 10794019 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 0 - flags: [may_store, produces_code] - scheduling_class: STORE - encoding_category: S - assembly_format: RS2_OFFSET_RS1 - - - id: 1031 - symbol: BEQ - name: BEQ - assembly_mnemonic: beq - encoding: 9699427 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [terminator, branch, produces_code] - scheduling_class: BRANCH - encoding_category: B - assembly_format: RS1_RS2_TARGET - - - id: 1032 - symbol: BNE - name: BNE - assembly_mnemonic: bne - encoding: 9703523 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [terminator, branch, produces_code] - scheduling_class: BRANCH - encoding_category: B - assembly_format: RS1_RS2_TARGET - - - id: 1033 - symbol: JAL - name: JAL - assembly_mnemonic: jal - encoding: 1135 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 1 - flags: [terminator, branch, produces_code] - scheduling_class: BRANCH - encoding_category: J - assembly_format: RD_TARGET - - - id: 1034 - symbol: ECALL - name: ECALL - assembly_mnemonic: ecall - encoding: 115 - operands: [] - num_explicit_defs: 0 - flags: [has_side_effects, produces_code] - scheduling_class: SYSTEM - encoding_category: SYSTEM - assembly_format: NONE - - - id: 1035 - symbol: EBREAK - name: EBREAK - assembly_mnemonic: ebreak - encoding: 1048691 - operands: [] - num_explicit_defs: 0 - flags: [has_side_effects, produces_code] - scheduling_class: SYSTEM - encoding_category: SYSTEM - assembly_format: NONE - - - id: 1036 - symbol: SLTI - name: SLTI - assembly_mnemonic: slti - encoding: 1352723 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1037 - symbol: SLTIU - name: SLTIU - assembly_mnemonic: sltiu - encoding: 1356819 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1038 - symbol: XORI - name: XORI - assembly_mnemonic: xori - encoding: 1360915 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1039 - symbol: ORI - name: ORI - assembly_mnemonic: ori - encoding: 1369107 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1040 - symbol: ANDI - name: ANDI - assembly_mnemonic: andi - encoding: 1373203 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1041 - symbol: SLLI - name: SLLI - assembly_mnemonic: slli - encoding: 1348627 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1247 - symbol: SH1ADD - name: SH1ADD - assembly_mnemonic: sh1add - encoding: 547660851 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1248 - symbol: SH2ADD - name: SH2ADD - assembly_mnemonic: sh2add - encoding: 547669043 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1249 - symbol: SH3ADD - name: SH3ADD - assembly_mnemonic: sh3add - encoding: 547677235 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1250 - symbol: SH1ADD_UW - name: SH1ADD_UW - assembly_mnemonic: sh1add.uw - encoding: 547660859 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1251 - symbol: SH2ADD_UW - name: SH2ADD_UW - assembly_mnemonic: sh2add.uw - encoding: 547669051 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1252 - symbol: SH3ADD_UW - name: SH3ADD_UW - assembly_mnemonic: sh3add.uw - encoding: 547677243 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1253 - symbol: SLLI_UW - name: SLLI_UW - assembly_mnemonic: slli.uw - encoding: 135566363 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1254 - symbol: ADD_UW - name: ADD_UW - assembly_mnemonic: add.uw - encoding: 144999483 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1255 - symbol: SEXT_B - name: SEXT_B - assembly_mnemonic: sext.b - encoding: 1615107091 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1 - - - id: 1256 - symbol: SEXT_H - name: SEXT_H - assembly_mnemonic: sext.h - encoding: 1616155667 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: I - assembly_format: RD_RS1 - - - id: 1257 - symbol: ZEXT_H_RV32 - name: ZEXT_H_RV32 - assembly_mnemonic: zext.h - encoding: 134530099 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1 - - - id: 1258 - symbol: ZEXT_H_RV64 - name: ZEXT_H_RV64 - assembly_mnemonic: zext.h - encoding: 134530107 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1 - - - id: 1259 - symbol: MIN - name: MIN - assembly_mnemonic: min - encoding: 178570291 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code, commutable] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1260 - symbol: MINU - name: MINU - assembly_mnemonic: minu - encoding: 178574387 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code, commutable] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1261 - symbol: MAX - name: MAX - assembly_mnemonic: max - encoding: 178578483 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code, commutable] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1262 - symbol: MAXU - name: MAXU - assembly_mnemonic: maxu - encoding: 178582579 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code, commutable] - scheduling_class: ALU - encoding_category: R - assembly_format: RD_RS1_RS2 - - - id: 1096 - symbol: LR_W - name: LR_W - assembly_mnemonic: lr.w - encoding: 268739631 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_PAREN_RS1 - - - id: 1097 - symbol: SC_W - name: SC_W - assembly_mnemonic: sc.w - encoding: 413443119 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1098 - symbol: AMOSWAP_W - name: AMOSWAP_W - assembly_mnemonic: amoswap.w - encoding: 145007663 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1118 - symbol: FLW - name: FLW - assembly_mnemonic: flw - encoding: 8692743 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, memory_role: value, name: FRD } - - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: I - assembly_format: FRD_OFFSET_RS1 - - - id: 1119 - symbol: FSW - name: FSW - assembly_mnemonic: fsw - encoding: 10789927 - operands: - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, memory_role: value, name: FRS2 } - - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 0 - flags: [may_store, produces_code] - scheduling_class: STORE - encoding_category: S - assembly_format: FRS2_OFFSET_RS1 - - - id: 1120 - symbol: FMADD_S - name: FMADD_S - assembly_mnemonic: fmadd.s - encoding: 1487176771 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS3 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R4 - assembly_format: FRD_FRS1_FRS2_FRS3_RM - - - id: 1121 - symbol: FMSUB_S - name: FMSUB_S - assembly_mnemonic: fmsub.s - encoding: 1487176775 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS3 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R4 - assembly_format: FRD_FRS1_FRS2_FRS3_RM - - - id: 1122 - symbol: FNMSUB_S - name: FNMSUB_S - assembly_mnemonic: fnmsub.s - encoding: 1487176779 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS3 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R4 - assembly_format: FRD_FRS1_FRS2_FRS3_RM - - - id: 1123 - symbol: FNMADD_S - name: FNMADD_S - assembly_mnemonic: fnmadd.s - encoding: 1487176783 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS3 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R4 - assembly_format: FRD_FRS1_FRS2_FRS3_RM - - - id: 1124 - symbol: FADD_S - name: FADD_S - assembly_mnemonic: fadd.s - encoding: 10781779 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2_RM - - - id: 1125 - symbol: FSUB_S - name: FSUB_S - assembly_mnemonic: fsub.s - encoding: 144999507 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2_RM - - - id: 1126 - symbol: FMUL_S - name: FMUL_S - assembly_mnemonic: fmul.s - encoding: 279217235 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R - assembly_format: FRD_FRS1_FRS2_RM - - - id: 1127 - symbol: FDIV_S - name: FDIV_S - assembly_mnemonic: fdiv.s - encoding: 413434963 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_DIV - encoding_category: R - assembly_format: FRD_FRS1_FRS2_RM - - - id: 1128 - symbol: FSQRT_S - name: FSQRT_S - assembly_mnemonic: fsqrt.s - encoding: 1476691027 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_SQRT - encoding_category: R - assembly_format: FRD_FRS1_RM - - - id: 1129 - symbol: FSGNJ_S - name: FSGNJ_S - assembly_mnemonic: fsgnj.s - encoding: 547652691 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1130 - symbol: FSGNJN_S - name: FSGNJN_S - assembly_mnemonic: fsgnjn.s - encoding: 547656787 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1131 - symbol: FSGNJX_S - name: FSGNJX_S - assembly_mnemonic: fsgnjx.s - encoding: 547660883 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1132 - symbol: FMIN_S - name: FMIN_S - assembly_mnemonic: fmin.s - encoding: 681870419 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1133 - symbol: FMAX_S - name: FMAX_S - assembly_mnemonic: fmax.s - encoding: 681874515 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1134 - symbol: FCVT_W_S - name: FCVT_W_S - assembly_mnemonic: fcvt.w.s - encoding: 3221521491 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1_RM - - - id: 1135 - symbol: FCVT_WU_S - name: FCVT_WU_S - assembly_mnemonic: fcvt.wu.s - encoding: 3222570067 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1_RM - - - id: 1136 - symbol: FCVT_L_S - name: FCVT_L_S - assembly_mnemonic: fcvt.l.s - encoding: 3223618643 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1_RM - - - id: 1137 - symbol: FCVT_LU_S - name: FCVT_LU_S - assembly_mnemonic: fcvt.lu.s - encoding: 3224667219 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1_RM - - - id: 1138 - symbol: FMV_X_W - name: FMV_X_W - assembly_mnemonic: fmv.x.w - encoding: 3758392403 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1 - - - id: 1139 - symbol: FEQ_S - name: FEQ_S - assembly_mnemonic: feq.s - encoding: 2695144531 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: RD_FRS1_FRS2 - - - id: 1140 - symbol: FLT_S - name: FLT_S - assembly_mnemonic: flt.s - encoding: 2695140435 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: RD_FRS1_FRS2 - - - id: 1141 - symbol: FLE_S - name: FLE_S - assembly_mnemonic: fle.s - encoding: 2695136339 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: RD_FRS1_FRS2 - - - id: 1142 - symbol: FCLASS_S - name: FCLASS_S - assembly_mnemonic: fclass.s - encoding: 3758396499 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1 - - - id: 1143 - symbol: FCVT_S_W - name: FCVT_S_W - assembly_mnemonic: fcvt.s.w - encoding: 3489956947 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1_RM - - - id: 1144 - symbol: FCVT_S_WU - name: FCVT_S_WU - assembly_mnemonic: fcvt.s.wu - encoding: 3491005523 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1_RM - - - id: 1145 - symbol: FCVT_S_L - name: FCVT_S_L - assembly_mnemonic: fcvt.s.l - encoding: 3492054099 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1_RM - - - id: 1146 - symbol: FCVT_S_LU - name: FCVT_S_LU - assembly_mnemonic: fcvt.s.lu - encoding: 3493102675 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1_RM - - - id: 1147 - symbol: FMV_W_X - name: FMV_W_X - assembly_mnemonic: fmv.w.x - encoding: 4026827859 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1 - - - id: 1148 - symbol: FLD - name: FLD - assembly_mnemonic: fld - encoding: 8696839 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRD } - - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: I - assembly_format: FRD_OFFSET_RS1 - - - id: 1149 - symbol: FSD - name: FSD - assembly_mnemonic: fsd - encoding: 10794023 - operands: - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRS2 } - - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } - num_explicit_defs: 0 - flags: [may_store, produces_code] - scheduling_class: STORE - encoding_category: S - assembly_format: FRS2_OFFSET_RS1 - - - id: 1150 - symbol: FMADD_D - name: FMADD_D - assembly_mnemonic: fmadd.d - encoding: 1520731203 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS3 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R4 - assembly_format: FRD_FRS1_FRS2_FRS3_RM - - - id: 1151 - symbol: FMSUB_D - name: FMSUB_D - assembly_mnemonic: fmsub.d - encoding: 1520731207 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS3 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R4 - assembly_format: FRD_FRS1_FRS2_FRS3_RM - - - id: 1152 - symbol: FNMSUB_D - name: FNMSUB_D - assembly_mnemonic: fnmsub.d - encoding: 1520731211 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS3 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R4 - assembly_format: FRD_FRS1_FRS2_FRS3_RM - - - id: 1153 - symbol: FNMADD_D - name: FNMADD_D - assembly_mnemonic: fnmadd.d - encoding: 1520731215 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS3 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R4 - assembly_format: FRD_FRS1_FRS2_FRS3_RM - - - id: 1154 - symbol: FADD_D - name: FADD_D - assembly_mnemonic: fadd.d - encoding: 44336211 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2_RM - - - id: 1155 - symbol: FSUB_D - name: FSUB_D - assembly_mnemonic: fsub.d - encoding: 178553939 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2_RM - - - id: 1156 - symbol: FMUL_D - name: FMUL_D - assembly_mnemonic: fmul.d - encoding: 312771667 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_MUL - encoding_category: R - assembly_format: FRD_FRS1_FRS2_RM - - - id: 1157 - symbol: FDIV_D - name: FDIV_D - assembly_mnemonic: fdiv.d - encoding: 446989395 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_DIV - encoding_category: R - assembly_format: FRD_FRS1_FRS2_RM - - - id: 1158 - symbol: FSQRT_D - name: FSQRT_D - assembly_mnemonic: fsqrt.d - encoding: 1510245459 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_SQRT - encoding_category: R - assembly_format: FRD_FRS1_RM - - - id: 1159 - symbol: FSGNJ_D - name: FSGNJ_D - assembly_mnemonic: fsgnj.d - encoding: 581207123 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1160 - symbol: FSGNJN_D - name: FSGNJN_D - assembly_mnemonic: fsgnjn.d - encoding: 581211219 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1161 - symbol: FSGNJX_D - name: FSGNJX_D - assembly_mnemonic: fsgnjx.d - encoding: 581215315 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1162 - symbol: FMIN_D - name: FMIN_D - assembly_mnemonic: fmin.d - encoding: 715424851 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1163 - symbol: FMAX_D - name: FMAX_D - assembly_mnemonic: fmax.d - encoding: 715428947 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: FRD_FRS1_FRS2 - - - id: 1164 - symbol: FCVT_W_D - name: FCVT_W_D - assembly_mnemonic: fcvt.w.d - encoding: 3255075923 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1_RM - - - id: 1165 - symbol: FCVT_WU_D - name: FCVT_WU_D - assembly_mnemonic: fcvt.wu.d - encoding: 3256124499 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1_RM - - - id: 1166 - symbol: FCVT_L_D - name: FCVT_L_D - assembly_mnemonic: fcvt.l.d - encoding: 3257173075 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1_RM - - - id: 1167 - symbol: FCVT_LU_D - name: FCVT_LU_D - assembly_mnemonic: fcvt.lu.d - encoding: 3258221651 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1_RM - - - id: 1168 - symbol: FMV_X_D - name: FMV_X_D - assembly_mnemonic: fmv.x.d - encoding: 3791946835 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1 - - - id: 1169 - symbol: FEQ_D - name: FEQ_D - assembly_mnemonic: feq.d - encoding: 2728698963 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: RD_FRS1_FRS2 - - - id: 1170 - symbol: FLT_D - name: FLT_D - assembly_mnemonic: flt.d - encoding: 2728694867 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: RD_FRS1_FRS2 - - - id: 1171 - symbol: FLE_D - name: FLE_D - assembly_mnemonic: fle.d - encoding: 2728690771 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } - num_explicit_defs: 1 - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_ADD - encoding_category: R - assembly_format: RD_FRS1_FRS2 - - - id: 1172 - symbol: FCLASS_D - name: FCLASS_D - assembly_mnemonic: fclass.d - encoding: 3791950931 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: RD_FRS1 - - - id: 1173 - symbol: FCVT_D_W - name: FCVT_D_W - assembly_mnemonic: fcvt.d.w - encoding: 3523511379 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1_RM - - - id: 1174 - symbol: FCVT_D_WU - name: FCVT_D_WU - assembly_mnemonic: fcvt.d.wu - encoding: 3524559955 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1_RM - - - id: 1175 - symbol: FCVT_D_L - name: FCVT_D_L - assembly_mnemonic: fcvt.d.l - encoding: 3525608531 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1_RM - - - id: 1176 - symbol: FCVT_D_LU - name: FCVT_D_LU - assembly_mnemonic: fcvt.d.lu - encoding: 3526657107 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1_RM - - - id: 1177 - symbol: FMV_D_X - name: FMV_D_X - assembly_mnemonic: fmv.d.x - encoding: 4060382291 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_RS1 - - - id: 1178 - symbol: FCVT_S_D - name: FCVT_S_D - assembly_mnemonic: fcvt.s.d - encoding: 1075086419 - operands: - - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_FRS1_RM - - - id: 1180 - symbol: C_ADDI4SPN - name: C_ADDI4SPN - assembly_mnemonic: c.addi4spn - encoding: 2048 - operands: - - { kinds: [register], role: def, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: C_UIMM10_NZ_A4, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - implicit_uses: [{ register: X2 }] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_IMM_SP - - - id: 1181 - symbol: C_FLD - name: C_FLD - assembly_mnemonic: c.fld - encoding: 9344 - operands: - - { kinds: [register], role: def, register_class: FPR64C, register_bank: FPR, memory_role: value, name: FRD } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: C_UIMM8_A8, name: IMM } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: C - assembly_format: FRD_OFFSET_RS1 - - - id: 1182 - symbol: C_LW - name: C_LW - assembly_mnemonic: c.lw - encoding: 17536 - operands: - - { kinds: [register], role: def, register_class: GPRC, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: C_UIMM7_A4, name: IMM } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: C - assembly_format: RD_OFFSET_RS1 - - - id: 1183 - symbol: C_LD - name: C_LD - assembly_mnemonic: c.ld - encoding: 25728 - operands: - - { kinds: [register], role: def, register_class: GPRC, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: C_UIMM8_A8, name: IMM } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: LOAD - encoding_category: C - assembly_format: RD_OFFSET_RS1 - - - id: 1184 - symbol: C_FSD - name: C_FSD - assembly_mnemonic: c.fsd - encoding: 42120 - operands: - - { kinds: [register], role: use, register_class: FPR64C, register_bank: FPR, memory_role: value, name: FRS2 } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: C_UIMM8_A8, name: IMM } - num_explicit_defs: 0 - flags: [may_store, produces_code] - scheduling_class: STORE - encoding_category: C - assembly_format: FRS2_OFFSET_RS1 - - - id: 1185 - symbol: C_SW - name: C_SW - assembly_mnemonic: c.sw - encoding: 50312 - operands: - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: C_UIMM7_A4, name: IMM } - num_explicit_defs: 0 - flags: [may_store, produces_code] - scheduling_class: STORE - encoding_category: C - assembly_format: RS2_OFFSET_RS1 - - - id: 1186 - symbol: C_SD - name: C_SD - assembly_mnemonic: c.sd - encoding: 58504 - operands: - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } - - { kinds: [immediate], immediate_predicate: C_UIMM8_A8, name: IMM } - num_explicit_defs: 0 - flags: [may_store, produces_code] - scheduling_class: STORE - encoding_category: C - assembly_format: RS2_OFFSET_RS1 - - - id: 1187 - symbol: C_ADDI - name: C_ADDI - assembly_mnemonic: c.addi - encoding: 1029 - operands: - - { kinds: [register], role: def_use, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: C_SIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_IMM - - - id: 1188 - symbol: C_ADDIW - name: C_ADDIW - assembly_mnemonic: c.addiw - encoding: 9221 - operands: - - { kinds: [register], role: def_use, register_class: GPR_NX0, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: C_SIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_IMM - - - id: 1189 - symbol: C_LI - name: C_LI - assembly_mnemonic: c.li - encoding: 17413 - operands: - - { kinds: [register], role: def, register_class: GPR_NX0, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: C_SIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_IMM - - - id: 1190 - symbol: C_ADDI16SP - name: C_ADDI16SP - assembly_mnemonic: c.addi16sp - encoding: 24897 - operands: - - { kinds: [immediate], immediate_predicate: C_SIMM10_A16_NZ, name: IMM } - num_explicit_defs: 0 - flags: [produces_code] - implicit_defs: [{ register: X2 }] - implicit_uses: [{ register: X2 }] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: IMM_SP - - - id: 1191 - symbol: C_LUI - name: C_LUI - assembly_mnemonic: c.lui - encoding: 25605 - operands: - - { kinds: [register], role: def, register_class: GPR_NX0_NX2, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: C_SIMM6_NZ, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_IMM - - - id: 1192 - symbol: C_SRLI - name: C_SRLI - assembly_mnemonic: c.srli - encoding: 32773 - operands: - - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_IMM - - - id: 1193 - symbol: C_SRAI - name: C_SRAI - assembly_mnemonic: c.srai - encoding: 33797 - operands: - - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_IMM - - - id: 1194 - symbol: C_ANDI - name: C_ANDI - assembly_mnemonic: c.andi - encoding: 34821 - operands: - - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: C_SIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_IMM - - - id: 1195 - symbol: C_SUB - name: C_SUB - assembly_mnemonic: c.sub - encoding: 35845 - operands: - - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_RS2 - - - id: 1196 - symbol: C_XOR - name: C_XOR - assembly_mnemonic: c.xor - encoding: 35877 - operands: - - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_RS2 - - - id: 1197 - symbol: C_OR - name: C_OR - assembly_mnemonic: c.or - encoding: 35909 - operands: - - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_RS2 - - - id: 1198 - symbol: C_AND - name: C_AND - assembly_mnemonic: c.and - encoding: 35941 - operands: - - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_RS2 - - - id: 1199 - symbol: C_SUBW - name: C_SUBW - assembly_mnemonic: c.subw - encoding: 39941 - operands: - - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_RS2 - - - id: 1200 - symbol: C_ADDW - name: C_ADDW - assembly_mnemonic: c.addw - encoding: 39973 - operands: - - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_RS2 - - - id: 1201 - symbol: C_J - name: C_J - assembly_mnemonic: c.j - encoding: 40961 - operands: - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [terminator, branch, produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: TARGET - - - id: 1202 - symbol: C_BEQZ - name: C_BEQZ - assembly_mnemonic: c.beqz - encoding: 49153 - operands: - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS1 } - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [terminator, branch, produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RS1_TARGET - - - id: 1203 - symbol: C_BNEZ - name: C_BNEZ - assembly_mnemonic: c.bnez - encoding: 57345 - operands: - - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS1 } - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [terminator, branch, produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RS1_TARGET - - - id: 1204 - symbol: C_SLLI - name: C_SLLI - assembly_mnemonic: c.slli - encoding: 1030 - operands: - - { kinds: [register], role: def_use, register_class: GPR_NX0, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_IMM - - - id: 1205 - symbol: C_FLDSP - name: C_FLDSP - assembly_mnemonic: c.fldsp - encoding: 9250 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRD } - - { kinds: [immediate], immediate_predicate: C_UIMM9_A8, name: IMM } - num_explicit_defs: 1 - flags: [may_load, produces_code] - implicit_uses: [{ register: X2 }] - scheduling_class: LOAD - encoding_category: C - assembly_format: FRD_OFFSET_SP - - - id: 1206 - symbol: C_LWSP - name: C_LWSP - assembly_mnemonic: c.lwsp - encoding: 17442 - operands: - - { kinds: [register], role: def, register_class: GPR_NX0, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [immediate], immediate_predicate: C_UIMM8_A4, name: IMM } - num_explicit_defs: 1 - flags: [may_load, produces_code] - implicit_uses: [{ register: X2 }] - scheduling_class: LOAD - encoding_category: C - assembly_format: RD_OFFSET_SP - - - id: 1207 - symbol: C_LDSP - name: C_LDSP - assembly_mnemonic: c.ldsp - encoding: 25634 - operands: - - { kinds: [register], role: def, register_class: GPR_NX0, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [immediate], immediate_predicate: C_UIMM9_A8, name: IMM } - num_explicit_defs: 1 - flags: [may_load, produces_code] - implicit_uses: [{ register: X2 }] - scheduling_class: LOAD - encoding_category: C - assembly_format: RD_OFFSET_SP - - - id: 1208 - symbol: C_JR - name: C_JR - assembly_mnemonic: c.jr - encoding: 33794 - operands: - - { kinds: [register], role: use, register_class: GPR_NX0, register_bank: GPR, name: RS1 } - num_explicit_defs: 0 - flags: [terminator, branch, indirect_branch, produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RS1 - - - id: 1209 - symbol: C_MV - name: C_MV - assembly_mnemonic: c.mv - encoding: 33830 - operands: - - { kinds: [register], role: def, register_class: GPR_NX0, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR_NX0, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_RS2 - - - id: 1210 - symbol: C_EBREAK - name: C_EBREAK - assembly_mnemonic: c.ebreak - encoding: 36866 - operands: [] - num_explicit_defs: 0 - flags: [has_side_effects, produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: NONE - - - id: 1211 - symbol: C_JALR - name: C_JALR - assembly_mnemonic: c.jalr - encoding: 37890 - operands: - - { kinds: [register], role: use, register_class: GPR_NX0, register_bank: GPR, name: RS1 } - num_explicit_defs: 0 - flags: [terminator, branch, indirect_branch, produces_code] - implicit_defs: [{ register: X1 }] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RS1 - - - id: 1212 - symbol: C_ADD - name: C_ADD - assembly_mnemonic: c.add - encoding: 37926 - operands: - - { kinds: [register], role: def_use, register_class: GPR_NX0, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR_NX0, register_bank: GPR, name: RS2 } - num_explicit_defs: 1 - flags: [produces_code] - scheduling_class: COMPRESSED - encoding_category: C - assembly_format: RD_RS2 - - - id: 1213 - symbol: C_FSDSP - name: C_FSDSP - assembly_mnemonic: c.fsdsp - encoding: 42018 - operands: - - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRS2 } - - { kinds: [immediate], immediate_predicate: C_UIMM9_A8, name: IMM } - num_explicit_defs: 0 - flags: [may_store, produces_code] - implicit_uses: [{ register: X2 }] - scheduling_class: STORE - encoding_category: C - assembly_format: FRS2_OFFSET_SP - - - id: 1214 - symbol: C_SWSP - name: C_SWSP - assembly_mnemonic: c.swsp - encoding: 50210 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [immediate], immediate_predicate: C_UIMM8_A4, name: IMM } - num_explicit_defs: 0 - flags: [may_store, produces_code] - implicit_uses: [{ register: X2 }] - scheduling_class: STORE - encoding_category: C - assembly_format: RS2_OFFSET_SP - - - id: 1215 - symbol: C_SDSP - name: C_SDSP - assembly_mnemonic: c.sdsp - encoding: 58402 - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [immediate], immediate_predicate: C_UIMM9_A8, name: IMM } - num_explicit_defs: 0 - flags: [may_store, produces_code] - implicit_uses: [{ register: X2 }] - scheduling_class: STORE - encoding_category: C - assembly_format: RS2_OFFSET_SP - - - id: 1179 - symbol: FCVT_D_S - name: FCVT_D_S - assembly_mnemonic: fcvt.d.s - encoding: 1107592275 - operands: - - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } - - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } - - { kinds: [immediate], immediate_predicate: RM, name: RM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [may_raise_fp_exception, produces_code] - scheduling_class: FP_CONVERT - encoding_category: R - assembly_format: FRD_FRS1_RM - - - id: 1099 - symbol: AMOADD_W - name: AMOADD_W - assembly_mnemonic: amoadd.w - encoding: 10789935 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1100 - symbol: AMOXOR_W - name: AMOXOR_W - assembly_mnemonic: amoxor.w - encoding: 547660847 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1101 - symbol: AMOAND_W - name: AMOAND_W - assembly_mnemonic: amoand.w - encoding: 1621402671 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1102 - symbol: AMOOR_W - name: AMOOR_W - assembly_mnemonic: amoor.w - encoding: 1084531759 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1103 - symbol: AMOMIN_W - name: AMOMIN_W - assembly_mnemonic: amomin.w - encoding: 2158273583 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1104 - symbol: AMOMAX_W - name: AMOMAX_W - assembly_mnemonic: amomax.w - encoding: 2695144495 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1105 - symbol: AMOMINU_W - name: AMOMINU_W - assembly_mnemonic: amominu.w - encoding: 3232015407 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1106 - symbol: AMOMAXU_W - name: AMOMAXU_W - assembly_mnemonic: amomaxu.w - encoding: 3768886319 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1107 - symbol: LR_D - name: LR_D - assembly_mnemonic: lr.d - encoding: 268743727 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_PAREN_RS1 - - - id: 1108 - symbol: SC_D - name: SC_D - assembly_mnemonic: sc.d - encoding: 413447215 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1109 - symbol: AMOSWAP_D - name: AMOSWAP_D - assembly_mnemonic: amoswap.d - encoding: 145011759 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1110 - symbol: AMOADD_D - name: AMOADD_D - assembly_mnemonic: amoadd.d - encoding: 10794031 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1111 - symbol: AMOXOR_D - name: AMOXOR_D - assembly_mnemonic: amoxor.d - encoding: 547664943 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1112 - symbol: AMOAND_D - name: AMOAND_D - assembly_mnemonic: amoand.d - encoding: 1621406767 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1113 - symbol: AMOOR_D - name: AMOOR_D - assembly_mnemonic: amoor.d - encoding: 1084535855 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1114 - symbol: AMOMIN_D - name: AMOMIN_D - assembly_mnemonic: amomin.d - encoding: 2158277679 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1115 - symbol: AMOMAX_D - name: AMOMAX_D - assembly_mnemonic: amomax.d - encoding: 2695148591 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1116 - symbol: AMOMINU_D - name: AMOMINU_D - assembly_mnemonic: amominu.d - encoding: 3232019503 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1117 - symbol: AMOMAXU_D - name: AMOMAXU_D - assembly_mnemonic: amomaxu.d - encoding: 3768890415 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } - num_explicit_defs: 1 - flags: [may_load, may_store, produces_code] - scheduling_class: ATOMIC - encoding_category: AMO - assembly_format: RD_RS2_PAREN_RS1 - - - id: 1229 - symbol: G_SLLW - name: G_SLLW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1230 - symbol: G_SRAW - name: G_SRAW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1231 - symbol: G_DIVW - name: G_DIVW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1232 - symbol: G_CLZW - name: G_CLZW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1233 - symbol: G_CTZW - name: G_CTZW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1234 - symbol: G_FCVT_W_RV64 - name: G_FCVT_W_RV64 - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 1 } - - { kinds: [immediate] } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1235 - symbol: G_FCLASS - name: G_FCLASS - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 1 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1236 - symbol: G_ROLW - name: G_ROLW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1237 - symbol: G_SRLW - name: G_SRLW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1238 - symbol: G_DIVUW - name: G_DIVUW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1239 - symbol: G_REMUW - name: G_REMUW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1240 - symbol: G_RORW - name: G_RORW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1241 - symbol: G_BREV8 - name: G_BREV8 - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1242 - symbol: G_FCVT_WU_RV64 - name: G_FCVT_WU_RV64 - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 1 } - - { kinds: [immediate] } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1243 - symbol: G_CLSW - name: G_CLSW - operands: - - { kinds: [register], role: def, type_index: 0 } - - { kinds: [register], role: use, type_index: 0 } - num_explicit_defs: 1 - flags: [generic, pseudo, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1244 - symbol: Select_GPR_Using_CC_GPR - name: Select_GPR_Using_CC_GPR - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } - - { kinds: [immediate] } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } - num_explicit_defs: 1 - flags: [pseudo, produces_code, allowed_pre_legalizer] - owner: instruction_select - deadline: selected - - - id: 1245 - symbol: ReadFFLAGS - name: ReadFFLAGS - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR } - num_explicit_defs: 1 - implicit_uses: [{ register: FFLAGS }] - flags: [pseudo, produces_code, allowed_pre_legalizer, has_side_effects] - owner: post_ra_expansion - deadline: post_ra_finalized - - - id: 1246 - symbol: WriteFFLAGS - name: WriteFFLAGS - operands: - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } - num_explicit_defs: 0 - implicit_defs: [{ register: FFLAGS }] - flags: [pseudo, produces_code, allowed_pre_legalizer, has_side_effects] - owner: post_ra_expansion - deadline: post_ra_finalized - - - id: 1217 - symbol: PseudoLOAD_STACK_ARG - name: PseudoLOAD_STACK_ARG - operands: - - { kinds: [register], role: def, memory_role: value } - - { kinds: [frame_index] } - - { kinds: [immediate, integer_immediate] } - - { kinds: [immediate] } - num_explicit_defs: 1 - flags: [pseudo, produces_code, allowed_pre_legalizer, may_load] - owner: instruction_select - deadline: selected - - - id: 1218 - symbol: PseudoSTORE_STACK_ARG - name: PseudoSTORE_STACK_ARG - operands: - - { kinds: [register], role: use, memory_role: value } - - { kinds: [frame_index] } - - { kinds: [immediate, integer_immediate] } - - { kinds: [immediate] } - num_explicit_defs: 0 - flags: [pseudo, produces_code, allowed_pre_legalizer, may_store] - owner: instruction_select - deadline: selected - - - id: 1219 - symbol: PseudoBYVAL_COPY - name: PseudoBYVAL_COPY - operands: - - { kinds: [register], role: def } - - { kinds: [register], role: use, memory_role: address } - - { kinds: [frame_index] } - - { kinds: [immediate, integer_immediate] } - - { kinds: [immediate, integer_immediate] } - num_explicit_defs: 1 - flags: [pseudo, produces_code, allowed_pre_legalizer, may_load, may_store] - owner: instruction_select - deadline: selected - - - id: 1220 - symbol: ADJCALLSTACKDOWN - name: ADJCALLSTACKDOWN - operands: - - { kinds: [immediate, integer_immediate] } - - { kinds: [immediate, integer_immediate] } - num_explicit_defs: 0 - implicit_defs: [{ register: X2 }] - implicit_uses: [{ register: X2 }] - flags: [pseudo, allowed_pre_legalizer, has_side_effects] - owner: prologue_epilogue_insertion - deadline: frame_finalized - - - id: 1221 - symbol: ADJCALLSTACKUP - name: ADJCALLSTACKUP - operands: - - { kinds: [immediate, integer_immediate] } - - { kinds: [immediate, integer_immediate] } - num_explicit_defs: 0 - implicit_defs: [{ register: X2 }] - implicit_uses: [{ register: X2 }] - flags: [pseudo, allowed_pre_legalizer, has_side_effects] - owner: prologue_epilogue_insertion - deadline: frame_finalized - - - id: 1222 - symbol: PseudoCALL - name: PseudoCALL - operands: - - { kinds: [global_symbol, external_symbol, register], role: use, allowed_target_flags: 1 } - - { kinds: [register_mask], optional: true } - num_explicit_defs: 0 - implicit_defs: [{ register: X1 }] - allow_extra_implicit_operands: true - flags: [pseudo, produces_code, allowed_pre_legalizer, call, may_load, may_store, has_side_effects, not_duplicable, unmodeled_side_effects] - size: 8 - owner: post_ra_expansion - deadline: post_ra_finalized - - - id: 1223 - symbol: PseudoTAIL - name: PseudoTAIL - operands: - - { kinds: [global_symbol, external_symbol, register], role: use, allowed_target_flags: 1 } - - { kinds: [register_mask], optional: true } - num_explicit_defs: 0 - allow_extra_implicit_operands: true - flags: [pseudo, produces_code, allowed_pre_legalizer, terminator, branch, call, barrier, may_load, may_store, has_side_effects, not_duplicable, unmodeled_side_effects] - size: 8 - owner: post_ra_expansion - deadline: post_ra_finalized - - - id: 1224 - symbol: PseudoRET - name: PseudoRET - operands: [] - num_explicit_defs: 0 - allow_extra_implicit_operands: true - flags: [pseudo, produces_code, allowed_pre_legalizer, terminator, return, barrier] - size: 4 - owner: post_ra_expansion - deadline: post_ra_finalized - - - id: 1225 - symbol: JALR_CALL - name: JALR_CALL - assembly_mnemonic: jalr - encoding: 1344615 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 4, name: IMM } - - { kinds: [register_mask] } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [call, may_load, may_store, has_side_effects, produces_code, not_duplicable, unmodeled_side_effects] - scheduling_class: BRANCH - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1226 - symbol: JALR_TAIL - name: JALR_TAIL - assembly_mnemonic: jalr - encoding: 1344615 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 4, name: IMM } - - { kinds: [register_mask] } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [terminator, branch, indirect_branch, call, barrier, may_load, may_store, has_side_effects, produces_code, not_duplicable, unmodeled_side_effects] - scheduling_class: BRANCH - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1227 - symbol: JALR_RET - name: JALR_RET - assembly_mnemonic: jalr - encoding: 1344615 - operands: - - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } - num_explicit_defs: 1 - allow_extra_implicit_operands: true - flags: [terminator, return, barrier, produces_code] - scheduling_class: BRANCH - encoding_category: I - assembly_format: RD_RS1_IMM - - - id: 1228 - symbol: PseudoBR - name: PseudoBR - operands: - - { kinds: [basic_block], name: TARGET } - num_explicit_defs: 0 - flags: [pseudo, produces_code, allowed_pre_legalizer, terminator, branch, barrier] - size: 4 - owner: post_ra_expansion - deadline: post_ra_finalized diff --git a/backend/lib/Target/RISCV/RISCVCallingConv.rccdesc b/backend/lib/Target/RISCV/RISCVCallingConv.rccdesc new file mode 100644 index 0000000..b222023 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVCallingConv.rccdesc @@ -0,0 +1,33 @@ +calling_conventions: + - + id: 2 + symbol: LP64 + name: lp64 + integer_register_class: GPR + floating_register_class: FPR64 + integer_argument_registers: [X10, X11, X12, X13, X14, X15, X16, X17] + floating_argument_registers: [] + integer_return_registers: [X10, X11] + floating_return_registers: [] + preserved_mask: CSR_ILP32_LP64 + stack_alignment_bytes: 16 + stack_argument_alignment_bytes: 16 + shadow_space_bytes: 0 + supports_varargs: true + supports_tail_calls: true + - + id: 1 + symbol: LP64D + name: lp64d + integer_register_class: GPR + floating_register_class: FPR64 + integer_argument_registers: [X10, X11, X12, X13, X14, X15, X16, X17] + floating_argument_registers: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D] + integer_return_registers: [X10, X11] + floating_return_registers: [F10_D, F11_D] + preserved_mask: CSR_ILP32D_LP64D + stack_alignment_bytes: 16 + stack_argument_alignment_bytes: 16 + shadow_space_bytes: 0 + supports_varargs: true + supports_tail_calls: true diff --git a/backend/lib/Target/RISCV/RISCVGISel.rccdesc b/backend/lib/Target/RISCV/RISCVGISel.rccdesc new file mode 100644 index 0000000..97ed3d6 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVGISel.rccdesc @@ -0,0 +1,157 @@ +selection_rules: + - + id: select_g_sllw + priority: 100 + match: + opcode: G_SLLW + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 64 } + - { index: 2, kind: scalar, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + - { index: 2, bank: GPR } + apply: { opcode: SLLW } + - + id: select_g_sraw + priority: 100 + match: + opcode: G_SRAW + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 64 } + - { index: 2, kind: scalar, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + - { index: 2, bank: GPR } + apply: { opcode: SRAW } + - + id: select_g_srlw + priority: 100 + match: + opcode: G_SRLW + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 64 } + - { index: 2, kind: scalar, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + - { index: 2, bank: GPR } + apply: { opcode: SRLW } + - + id: select_g_divw + priority: 100 + match: + opcode: G_DIVW + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 64 } + - { index: 2, kind: scalar, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + - { index: 2, bank: GPR } + apply: { opcode: DIVW } + - + id: select_g_divuw + priority: 100 + match: + opcode: G_DIVUW + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 64 } + - { index: 2, kind: scalar, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + - { index: 2, bank: GPR } + apply: { opcode: DIVUW } + - + id: select_g_remuw + priority: 100 + match: + opcode: G_REMUW + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 64 } + - { index: 2, kind: scalar, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + - { index: 2, bank: GPR } + apply: { opcode: REMUW } + - + id: select_g_fcvt_w_rv64_s32 + priority: 100 + match: + opcode: G_FCVT_W_RV64 + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 32 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: FPR } + apply: { opcode: FCVT_W_S } + - + id: select_g_fcvt_w_rv64_s64 + priority: 100 + match: + opcode: G_FCVT_W_RV64 + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: FPR } + apply: { opcode: FCVT_W_D } + - + id: select_g_fcvt_wu_rv64_s32 + priority: 100 + match: + opcode: G_FCVT_WU_RV64 + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 32 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: FPR } + apply: { opcode: FCVT_WU_S } + - + id: select_g_fcvt_wu_rv64_s64 + priority: 100 + match: + opcode: G_FCVT_WU_RV64 + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: FPR } + apply: { opcode: FCVT_WU_D } + - + id: select_g_fclass_s32 + priority: 100 + match: + opcode: G_FCLASS + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 32 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: FPR } + apply: { opcode: FCLASS_S } + - + id: select_g_fclass_s64 + priority: 100 + match: + opcode: G_FCLASS + result_type: { kind: scalar, bits: 64 } + operand_types: + - { index: 1, kind: scalar, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: FPR } + apply: { opcode: FCLASS_D } diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoA.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoA.rccdesc new file mode 100644 index 0000000..c954f8e --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoA.rccdesc @@ -0,0 +1,329 @@ +instructions: + - + id: 1096 + symbol: LR_W + name: LR_W + assembly_mnemonic: lr.w + encoding: 268739631 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_PAREN_RS1 + - + id: 1097 + symbol: SC_W + name: SC_W + assembly_mnemonic: sc.w + encoding: 413443119 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1098 + symbol: AMOSWAP_W + name: AMOSWAP_W + assembly_mnemonic: amoswap.w + encoding: 145007663 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1099 + symbol: AMOADD_W + name: AMOADD_W + assembly_mnemonic: amoadd.w + encoding: 10789935 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1100 + symbol: AMOXOR_W + name: AMOXOR_W + assembly_mnemonic: amoxor.w + encoding: 547660847 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1101 + symbol: AMOAND_W + name: AMOAND_W + assembly_mnemonic: amoand.w + encoding: 1621402671 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1102 + symbol: AMOOR_W + name: AMOOR_W + assembly_mnemonic: amoor.w + encoding: 1084531759 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1103 + symbol: AMOMIN_W + name: AMOMIN_W + assembly_mnemonic: amomin.w + encoding: 2158273583 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1104 + symbol: AMOMAX_W + name: AMOMAX_W + assembly_mnemonic: amomax.w + encoding: 2695144495 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1105 + symbol: AMOMINU_W + name: AMOMINU_W + assembly_mnemonic: amominu.w + encoding: 3232015407 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1106 + symbol: AMOMAXU_W + name: AMOMAXU_W + assembly_mnemonic: amomaxu.w + encoding: 3768886319 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1107 + symbol: LR_D + name: LR_D + assembly_mnemonic: lr.d + encoding: 268743727 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_PAREN_RS1 + - + id: 1108 + symbol: SC_D + name: SC_D + assembly_mnemonic: sc.d + encoding: 413447215 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1109 + symbol: AMOSWAP_D + name: AMOSWAP_D + assembly_mnemonic: amoswap.d + encoding: 145011759 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1110 + symbol: AMOADD_D + name: AMOADD_D + assembly_mnemonic: amoadd.d + encoding: 10794031 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1111 + symbol: AMOXOR_D + name: AMOXOR_D + assembly_mnemonic: amoxor.d + encoding: 547664943 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1112 + symbol: AMOAND_D + name: AMOAND_D + assembly_mnemonic: amoand.d + encoding: 1621406767 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1113 + symbol: AMOOR_D + name: AMOOR_D + assembly_mnemonic: amoor.d + encoding: 1084535855 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1114 + symbol: AMOMIN_D + name: AMOMIN_D + assembly_mnemonic: amomin.d + encoding: 2158277679 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1115 + symbol: AMOMAX_D + name: AMOMAX_D + assembly_mnemonic: amomax.d + encoding: 2695148591 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1116 + symbol: AMOMINU_D + name: AMOMINU_D + assembly_mnemonic: amominu.d + encoding: 3232019503 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 + - + id: 1117 + symbol: AMOMAXU_D + name: AMOMAXU_D + assembly_mnemonic: amomaxu.d + encoding: 3768890415 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + num_explicit_defs: 1 + flags: [may_load, may_store, produces_code] + scheduling_class: ATOMIC + encoding_category: AMO + assembly_format: RD_RS2_PAREN_RS1 diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoBase.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoBase.rccdesc new file mode 100644 index 0000000..e1e84d0 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoBase.rccdesc @@ -0,0 +1,100 @@ +named_operands: + - { id: 1, symbol: RD, name: rd } + - { id: 2, symbol: RS1, name: rs1 } + - { id: 3, symbol: RS2, name: rs2 } + - { id: 4, symbol: IMM, name: imm } + - { id: 5, symbol: TARGET, name: target } + - { id: 6, symbol: CSR, name: csr } + - { id: 7, symbol: ZIMM, name: zimm } + - { id: 8, symbol: PRED, name: pred } + - { id: 9, symbol: SUCC, name: succ } + - { id: 10, symbol: FRD, name: frd } + - { id: 11, symbol: FRS1, name: frs1 } + - { id: 12, symbol: FRS2, name: frs2 } + - { id: 13, symbol: FRS3, name: frs3 } + - { id: 14, symbol: RM, name: rm } + +immediate_predicates: + - { id: 1, symbol: SIMM12, name: simm12, kind: signed, bits: 12 } + - { id: 2, symbol: UIMM20, name: uimm20, kind: unsigned, bits: 20 } + - { id: 3, symbol: UIMM5, name: uimm5, kind: unsigned, bits: 5 } + - { id: 4, symbol: UIMM6, name: uimm6, kind: unsigned, bits: 6 } + - { id: 5, symbol: UIMM12, name: uimm12, kind: unsigned, bits: 12 } + - { id: 6, symbol: UIMM4, name: uimm4, kind: unsigned, bits: 4 } + - { id: 7, symbol: RM, name: rm, kind: unsigned, bits: 3, allowed_values: [0, 1, 2, 3, 4, 7] } + - { id: 8, symbol: C_UIMM10_NZ_A4, name: c-uimm10-nz-a4, kind: unsigned, bits: 10, alignment: 4, nonzero: true } + - { id: 9, symbol: C_UIMM7_A4, name: c-uimm7-a4, kind: unsigned, bits: 7, alignment: 4 } + - { id: 10, symbol: C_UIMM8_A8, name: c-uimm8-a8, kind: unsigned, bits: 8, alignment: 8 } + - { id: 11, symbol: C_UIMM8_A4, name: c-uimm8-a4, kind: unsigned, bits: 8, alignment: 4 } + - { id: 12, symbol: C_UIMM9_A8, name: c-uimm9-a8, kind: unsigned, bits: 9, alignment: 8 } + - { id: 13, symbol: C_SIMM6, name: c-simm6, kind: signed, bits: 6 } + - { id: 14, symbol: C_SIMM6_NZ, name: c-simm6-nz, kind: signed, bits: 6, nonzero: true } + - { id: 15, symbol: C_SIMM9_A2, name: c-simm9-a2, kind: signed, bits: 9, alignment: 2 } + - { id: 16, symbol: C_SIMM12_A2, name: c-simm12-a2, kind: signed, bits: 12, alignment: 2 } + - { id: 17, symbol: C_SIMM10_A16_NZ, name: c-simm10-a16-nz, kind: signed, bits: 10, alignment: 16, nonzero: true } + +scheduling_classes: + - { id: 1, symbol: ALU, name: alu, micro_ops: 1, latency: 1 } + - { id: 2, symbol: LOAD, name: load, micro_ops: 1, latency: 3 } + - { id: 3, symbol: STORE, name: store, micro_ops: 1, latency: 1 } + - { id: 4, symbol: BRANCH, name: branch, micro_ops: 1, latency: 1 } + - { id: 5, symbol: SYSTEM, name: system, micro_ops: 1, latency: 1 } + - { id: 6, symbol: MUL, name: mul, micro_ops: 1, latency: 3 } + - { id: 7, symbol: DIV, name: div, micro_ops: 1, latency: 20 } + - { id: 8, symbol: FENCE, name: fence, micro_ops: 1, latency: 1 } + - { id: 9, symbol: ATOMIC, name: atomic, micro_ops: 1, latency: 4 } + - { id: 10, symbol: FP_ADD, name: fp-add, micro_ops: 1, latency: 4 } + - { id: 11, symbol: FP_MUL, name: fp-mul, micro_ops: 1, latency: 4 } + - { id: 12, symbol: FP_DIV, name: fp-div, micro_ops: 1, latency: 20 } + - { id: 13, symbol: FP_SQRT, name: fp-sqrt, micro_ops: 1, latency: 20 } + - { id: 14, symbol: FP_CONVERT, name: fp-convert, micro_ops: 1, latency: 4 } + - { id: 15, symbol: COMPRESSED, name: compressed, micro_ops: 1, latency: 1 } + +encoding_categories: + - { id: 1, symbol: R, name: r, size_bytes: 4 } + - { id: 2, symbol: I, name: i, size_bytes: 4 } + - { id: 3, symbol: S, name: s, size_bytes: 4 } + - { id: 4, symbol: B, name: b, size_bytes: 4 } + - { id: 5, symbol: U, name: u, size_bytes: 4 } + - { id: 6, symbol: J, name: j, size_bytes: 4 } + - { id: 7, symbol: SYSTEM, name: system, size_bytes: 4 } + - { id: 8, symbol: AMO, name: amo, size_bytes: 4 } + - { id: 9, symbol: R4, name: r4, size_bytes: 4 } + - { id: 10, symbol: C, name: c, size_bytes: 2 } + +assembly_formats: + - { id: 1, symbol: RD_IMM, name: rd-imm } + - { id: 2, symbol: RD_RS1_IMM, name: rd-rs1-imm } + - { id: 3, symbol: RD_RS1_RS2, name: rd-rs1-rs2 } + - { id: 4, symbol: RD_OFFSET_RS1, name: rd-offset-rs1 } + - { id: 5, symbol: RS2_OFFSET_RS1, name: rs2-offset-rs1 } + - { id: 6, symbol: RS1_RS2_TARGET, name: rs1-rs2-target } + - { id: 7, symbol: RD_TARGET, name: rd-target } + - { id: 8, symbol: NONE, name: none } + - { id: 9, symbol: IMM_IMM, name: imm-imm } + - { id: 10, symbol: RD_CSR_RS1, name: rd-csr-rs1 } + - { id: 11, symbol: RD_CSR_IMM, name: rd-csr-imm } + - { id: 12, symbol: RD_PAREN_RS1, name: rd-paren-rs1 } + - { id: 13, symbol: RD_RS2_PAREN_RS1, name: rd-rs2-paren-rs1 } + - { id: 14, symbol: FRD_OFFSET_RS1, name: frd-offset-rs1 } + - { id: 15, symbol: FRS2_OFFSET_RS1, name: frs2-offset-rs1 } + - { id: 16, symbol: FRD_FRS1_FRS2_RM, name: frd-frs1-frs2-rm } + - { id: 17, symbol: FRD_FRS1_FRS2_FRS3_RM, name: frd-frs1-frs2-frs3-rm } + - { id: 18, symbol: FRD_FRS1_RM, name: frd-frs1-rm } + - { id: 19, symbol: FRD_FRS1_FRS2, name: frd-frs1-frs2 } + - { id: 20, symbol: RD_FRS1_RM, name: rd-frs1-rm } + - { id: 21, symbol: RD_FRS1, name: rd-frs1 } + - { id: 22, symbol: RD_FRS1_FRS2, name: rd-frs1-frs2 } + - { id: 23, symbol: FRD_RS1_RM, name: frd-rs1-rm } + - { id: 24, symbol: FRD_RS1, name: frd-rs1 } + - { id: 25, symbol: TARGET, name: target } + - { id: 26, symbol: RS1_TARGET, name: rs1-target } + - { id: 27, symbol: RS1, name: rs1 } + - { id: 28, symbol: RD_RS2, name: rd-rs2 } + - { id: 29, symbol: IMM_SP, name: imm-sp } + - { id: 30, symbol: RD_IMM_SP, name: rd-imm-sp } + - { id: 31, symbol: RD_OFFSET_SP, name: rd-offset-sp } + - { id: 32, symbol: RS2_OFFSET_SP, name: rs2-offset-sp } + - { id: 33, symbol: FRD_OFFSET_SP, name: frd-offset-sp } + - { id: 34, symbol: FRS2_OFFSET_SP, name: frs2-offset-sp } + - { id: 35, symbol: RD_RS1, name: rd-rs1 } diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc new file mode 100644 index 0000000..fa1b75a --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc @@ -0,0 +1,515 @@ +instructions: + - + id: 1180 + symbol: C_ADDI4SPN + name: C_ADDI4SPN + assembly_mnemonic: c.addi4spn + encoding: 2048 + operands: + - { kinds: [register], role: def, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: C_UIMM10_NZ_A4, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + implicit_uses: [{ register: X2 }] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_IMM_SP + - + id: 1181 + symbol: C_FLD + name: C_FLD + assembly_mnemonic: c.fld + encoding: 9344 + operands: + - { kinds: [register], role: def, register_class: FPR64C, register_bank: FPR, memory_role: value, name: FRD } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate], immediate_predicate: C_UIMM8_A8, name: IMM } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: C + assembly_format: FRD_OFFSET_RS1 + - + id: 1182 + symbol: C_LW + name: C_LW + assembly_mnemonic: c.lw + encoding: 17536 + operands: + - { kinds: [register], role: def, register_class: GPRC, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate], immediate_predicate: C_UIMM7_A4, name: IMM } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: C + assembly_format: RD_OFFSET_RS1 + - + id: 1183 + symbol: C_LD + name: C_LD + assembly_mnemonic: c.ld + encoding: 25728 + operands: + - { kinds: [register], role: def, register_class: GPRC, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate], immediate_predicate: C_UIMM8_A8, name: IMM } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: C + assembly_format: RD_OFFSET_RS1 + - + id: 1184 + symbol: C_FSD + name: C_FSD + assembly_mnemonic: c.fsd + encoding: 42120 + operands: + - { kinds: [register], role: use, register_class: FPR64C, register_bank: FPR, memory_role: value, name: FRS2 } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate], immediate_predicate: C_UIMM8_A8, name: IMM } + num_explicit_defs: 0 + flags: [may_store, produces_code] + scheduling_class: STORE + encoding_category: C + assembly_format: FRS2_OFFSET_RS1 + - + id: 1185 + symbol: C_SW + name: C_SW + assembly_mnemonic: c.sw + encoding: 50312 + operands: + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate], immediate_predicate: C_UIMM7_A4, name: IMM } + num_explicit_defs: 0 + flags: [may_store, produces_code] + scheduling_class: STORE + encoding_category: C + assembly_format: RS2_OFFSET_RS1 + - + id: 1186 + symbol: C_SD + name: C_SD + assembly_mnemonic: c.sd + encoding: 58504 + operands: + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate], immediate_predicate: C_UIMM8_A8, name: IMM } + num_explicit_defs: 0 + flags: [may_store, produces_code] + scheduling_class: STORE + encoding_category: C + assembly_format: RS2_OFFSET_RS1 + - + id: 1187 + symbol: C_ADDI + name: C_ADDI + assembly_mnemonic: c.addi + encoding: 1029 + operands: + - { kinds: [register], role: def_use, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: C_SIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_IMM + - + id: 1188 + symbol: C_ADDIW + name: C_ADDIW + assembly_mnemonic: c.addiw + encoding: 9221 + operands: + - { kinds: [register], role: def_use, register_class: GPR_NX0, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: C_SIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_IMM + - + id: 1189 + symbol: C_LI + name: C_LI + assembly_mnemonic: c.li + encoding: 17413 + operands: + - { kinds: [register], role: def, register_class: GPR_NX0, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: C_SIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_IMM + - + id: 1190 + symbol: C_ADDI16SP + name: C_ADDI16SP + assembly_mnemonic: c.addi16sp + encoding: 24897 + operands: + - { kinds: [immediate], immediate_predicate: C_SIMM10_A16_NZ, name: IMM } + num_explicit_defs: 0 + flags: [produces_code] + implicit_defs: [{ register: X2 }] + implicit_uses: [{ register: X2 }] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: IMM_SP + - + id: 1191 + symbol: C_LUI + name: C_LUI + assembly_mnemonic: c.lui + encoding: 25605 + operands: + - { kinds: [register], role: def, register_class: GPR_NX0_NX2, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: C_SIMM6_NZ, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_IMM + - + id: 1192 + symbol: C_SRLI + name: C_SRLI + assembly_mnemonic: c.srli + encoding: 32773 + operands: + - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_IMM + - + id: 1193 + symbol: C_SRAI + name: C_SRAI + assembly_mnemonic: c.srai + encoding: 33797 + operands: + - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_IMM + - + id: 1194 + symbol: C_ANDI + name: C_ANDI + assembly_mnemonic: c.andi + encoding: 34821 + operands: + - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: C_SIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_IMM + - + id: 1195 + symbol: C_SUB + name: C_SUB + assembly_mnemonic: c.sub + encoding: 35845 + operands: + - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 + - + id: 1196 + symbol: C_XOR + name: C_XOR + assembly_mnemonic: c.xor + encoding: 35877 + operands: + - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 + - + id: 1197 + symbol: C_OR + name: C_OR + assembly_mnemonic: c.or + encoding: 35909 + operands: + - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 + - + id: 1198 + symbol: C_AND + name: C_AND + assembly_mnemonic: c.and + encoding: 35941 + operands: + - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 + - + id: 1199 + symbol: C_SUBW + name: C_SUBW + assembly_mnemonic: c.subw + encoding: 39941 + operands: + - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 + - + id: 1200 + symbol: C_ADDW + name: C_ADDW + assembly_mnemonic: c.addw + encoding: 39973 + operands: + - { kinds: [register], role: def_use, register_class: GPRC, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 + - + id: 1201 + symbol: C_J + name: C_J + assembly_mnemonic: c.j + encoding: 40961 + operands: + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [terminator, branch, produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: TARGET + - + id: 1202 + symbol: C_BEQZ + name: C_BEQZ + assembly_mnemonic: c.beqz + encoding: 49153 + operands: + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS1 } + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [terminator, branch, produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RS1_TARGET + - + id: 1203 + symbol: C_BNEZ + name: C_BNEZ + assembly_mnemonic: c.bnez + encoding: 57345 + operands: + - { kinds: [register], role: use, register_class: GPRC, register_bank: GPR, name: RS1 } + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [terminator, branch, produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RS1_TARGET + - + id: 1204 + symbol: C_SLLI + name: C_SLLI + assembly_mnemonic: c.slli + encoding: 1030 + operands: + - { kinds: [register], role: def_use, register_class: GPR_NX0, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_IMM + - + id: 1205 + symbol: C_FLDSP + name: C_FLDSP + assembly_mnemonic: c.fldsp + encoding: 9250 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRD } + - { kinds: [immediate], immediate_predicate: C_UIMM9_A8, name: IMM } + num_explicit_defs: 1 + flags: [may_load, produces_code] + implicit_uses: [{ register: X2 }] + scheduling_class: LOAD + encoding_category: C + assembly_format: FRD_OFFSET_SP + - + id: 1206 + symbol: C_LWSP + name: C_LWSP + assembly_mnemonic: c.lwsp + encoding: 17442 + operands: + - { kinds: [register], role: def, register_class: GPR_NX0, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [immediate], immediate_predicate: C_UIMM8_A4, name: IMM } + num_explicit_defs: 1 + flags: [may_load, produces_code] + implicit_uses: [{ register: X2 }] + scheduling_class: LOAD + encoding_category: C + assembly_format: RD_OFFSET_SP + - + id: 1207 + symbol: C_LDSP + name: C_LDSP + assembly_mnemonic: c.ldsp + encoding: 25634 + operands: + - { kinds: [register], role: def, register_class: GPR_NX0, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [immediate], immediate_predicate: C_UIMM9_A8, name: IMM } + num_explicit_defs: 1 + flags: [may_load, produces_code] + implicit_uses: [{ register: X2 }] + scheduling_class: LOAD + encoding_category: C + assembly_format: RD_OFFSET_SP + - + id: 1208 + symbol: C_JR + name: C_JR + assembly_mnemonic: c.jr + encoding: 33794 + operands: + - { kinds: [register], role: use, register_class: GPR_NX0, register_bank: GPR, name: RS1 } + num_explicit_defs: 0 + flags: [terminator, branch, indirect_branch, produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RS1 + - + id: 1209 + symbol: C_MV + name: C_MV + assembly_mnemonic: c.mv + encoding: 33830 + operands: + - { kinds: [register], role: def, register_class: GPR_NX0, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR_NX0, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 + - + id: 1210 + symbol: C_EBREAK + name: C_EBREAK + assembly_mnemonic: c.ebreak + encoding: 36866 + operands: [] + num_explicit_defs: 0 + flags: [has_side_effects, produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: NONE + - + id: 1211 + symbol: C_JALR + name: C_JALR + assembly_mnemonic: c.jalr + encoding: 37890 + operands: + - { kinds: [register], role: use, register_class: GPR_NX0, register_bank: GPR, name: RS1 } + num_explicit_defs: 0 + flags: [terminator, branch, indirect_branch, produces_code] + implicit_defs: [{ register: X1 }] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RS1 + - + id: 1212 + symbol: C_ADD + name: C_ADD + assembly_mnemonic: c.add + encoding: 37926 + operands: + - { kinds: [register], role: def_use, register_class: GPR_NX0, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR_NX0, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 + - + id: 1213 + symbol: C_FSDSP + name: C_FSDSP + assembly_mnemonic: c.fsdsp + encoding: 42018 + operands: + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRS2 } + - { kinds: [immediate], immediate_predicate: C_UIMM9_A8, name: IMM } + num_explicit_defs: 0 + flags: [may_store, produces_code] + implicit_uses: [{ register: X2 }] + scheduling_class: STORE + encoding_category: C + assembly_format: FRS2_OFFSET_SP + - + id: 1214 + symbol: C_SWSP + name: C_SWSP + assembly_mnemonic: c.swsp + encoding: 50210 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [immediate], immediate_predicate: C_UIMM8_A4, name: IMM } + num_explicit_defs: 0 + flags: [may_store, produces_code] + implicit_uses: [{ register: X2 }] + scheduling_class: STORE + encoding_category: C + assembly_format: RS2_OFFSET_SP + - + id: 1215 + symbol: C_SDSP + name: C_SDSP + assembly_mnemonic: c.sdsp + encoding: 58402 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [immediate], immediate_predicate: C_UIMM9_A8, name: IMM } + num_explicit_defs: 0 + flags: [may_store, produces_code] + implicit_uses: [{ register: X2 }] + scheduling_class: STORE + encoding_category: C + assembly_format: RS2_OFFSET_SP diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoD.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoD.rccdesc new file mode 100644 index 0000000..15e4ab1 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoD.rccdesc @@ -0,0 +1,509 @@ +instructions: + - + id: 1148 + symbol: FLD + name: FLD + assembly_mnemonic: fld + encoding: 8696839 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRD } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: I + assembly_format: FRD_OFFSET_RS1 + - + id: 1149 + symbol: FSD + name: FSD + assembly_mnemonic: fsd + encoding: 10794023 + operands: + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, memory_role: value, name: FRS2 } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 0 + flags: [may_store, produces_code] + scheduling_class: STORE + encoding_category: S + assembly_format: FRS2_OFFSET_RS1 + - + id: 1150 + symbol: FMADD_D + name: FMADD_D + assembly_mnemonic: fmadd.d + encoding: 1520731203 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS3 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R4 + assembly_format: FRD_FRS1_FRS2_FRS3_RM + - + id: 1151 + symbol: FMSUB_D + name: FMSUB_D + assembly_mnemonic: fmsub.d + encoding: 1520731207 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS3 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R4 + assembly_format: FRD_FRS1_FRS2_FRS3_RM + - + id: 1152 + symbol: FNMSUB_D + name: FNMSUB_D + assembly_mnemonic: fnmsub.d + encoding: 1520731211 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS3 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R4 + assembly_format: FRD_FRS1_FRS2_FRS3_RM + - + id: 1153 + symbol: FNMADD_D + name: FNMADD_D + assembly_mnemonic: fnmadd.d + encoding: 1520731215 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS3 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R4 + assembly_format: FRD_FRS1_FRS2_FRS3_RM + - + id: 1154 + symbol: FADD_D + name: FADD_D + assembly_mnemonic: fadd.d + encoding: 44336211 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2_RM + - + id: 1155 + symbol: FSUB_D + name: FSUB_D + assembly_mnemonic: fsub.d + encoding: 178553939 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2_RM + - + id: 1156 + symbol: FMUL_D + name: FMUL_D + assembly_mnemonic: fmul.d + encoding: 312771667 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R + assembly_format: FRD_FRS1_FRS2_RM + - + id: 1157 + symbol: FDIV_D + name: FDIV_D + assembly_mnemonic: fdiv.d + encoding: 446989395 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_DIV + encoding_category: R + assembly_format: FRD_FRS1_FRS2_RM + - + id: 1158 + symbol: FSQRT_D + name: FSQRT_D + assembly_mnemonic: fsqrt.d + encoding: 1510245459 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_SQRT + encoding_category: R + assembly_format: FRD_FRS1_RM + - + id: 1159 + symbol: FSGNJ_D + name: FSGNJ_D + assembly_mnemonic: fsgnj.d + encoding: 581207123 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1160 + symbol: FSGNJN_D + name: FSGNJN_D + assembly_mnemonic: fsgnjn.d + encoding: 581211219 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1161 + symbol: FSGNJX_D + name: FSGNJX_D + assembly_mnemonic: fsgnjx.d + encoding: 581215315 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1162 + symbol: FMIN_D + name: FMIN_D + assembly_mnemonic: fmin.d + encoding: 715424851 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1163 + symbol: FMAX_D + name: FMAX_D + assembly_mnemonic: fmax.d + encoding: 715428947 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1164 + symbol: FCVT_W_D + name: FCVT_W_D + assembly_mnemonic: fcvt.w.d + encoding: 3255075923 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1_RM + - + id: 1165 + symbol: FCVT_WU_D + name: FCVT_WU_D + assembly_mnemonic: fcvt.wu.d + encoding: 3256124499 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1_RM + - + id: 1166 + symbol: FCVT_L_D + name: FCVT_L_D + assembly_mnemonic: fcvt.l.d + encoding: 3257173075 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1_RM + - + id: 1167 + symbol: FCVT_LU_D + name: FCVT_LU_D + assembly_mnemonic: fcvt.lu.d + encoding: 3258221651 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1_RM + - + id: 1168 + symbol: FMV_X_D + name: FMV_X_D + assembly_mnemonic: fmv.x.d + encoding: 3791946835 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1 + - + id: 1169 + symbol: FEQ_D + name: FEQ_D + assembly_mnemonic: feq.d + encoding: 2728698963 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: RD_FRS1_FRS2 + - + id: 1170 + symbol: FLT_D + name: FLT_D + assembly_mnemonic: flt.d + encoding: 2728694867 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: RD_FRS1_FRS2 + - + id: 1171 + symbol: FLE_D + name: FLE_D + assembly_mnemonic: fle.d + encoding: 2728690771 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: RD_FRS1_FRS2 + - + id: 1172 + symbol: FCLASS_D + name: FCLASS_D + assembly_mnemonic: fclass.d + encoding: 3791950931 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1 + - + id: 1173 + symbol: FCVT_D_W + name: FCVT_D_W + assembly_mnemonic: fcvt.d.w + encoding: 3523511379 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1_RM + - + id: 1174 + symbol: FCVT_D_WU + name: FCVT_D_WU + assembly_mnemonic: fcvt.d.wu + encoding: 3524559955 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1_RM + - + id: 1175 + symbol: FCVT_D_L + name: FCVT_D_L + assembly_mnemonic: fcvt.d.l + encoding: 3525608531 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1_RM + - + id: 1176 + symbol: FCVT_D_LU + name: FCVT_D_LU + assembly_mnemonic: fcvt.d.lu + encoding: 3526657107 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1_RM + - + id: 1177 + symbol: FMV_D_X + name: FMV_D_X + assembly_mnemonic: fmv.d.x + encoding: 4060382291 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1 + - + id: 1178 + symbol: FCVT_S_D + name: FCVT_S_D + assembly_mnemonic: fcvt.s.d + encoding: 1075086419 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_FRS1_RM + - + id: 1179 + symbol: FCVT_D_S + name: FCVT_D_S + assembly_mnemonic: fcvt.d.s + encoding: 1107592275 + operands: + - { kinds: [register], role: def, register_class: FPR64, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_FRS1_RM diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoF.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoF.rccdesc new file mode 100644 index 0000000..3149207 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoF.rccdesc @@ -0,0 +1,477 @@ +instructions: + - + id: 1118 + symbol: FLW + name: FLW + assembly_mnemonic: flw + encoding: 8692743 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, memory_role: value, name: FRD } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: I + assembly_format: FRD_OFFSET_RS1 + - + id: 1119 + symbol: FSW + name: FSW + assembly_mnemonic: fsw + encoding: 10789927 + operands: + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, memory_role: value, name: FRS2 } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 0 + flags: [may_store, produces_code] + scheduling_class: STORE + encoding_category: S + assembly_format: FRS2_OFFSET_RS1 + - + id: 1120 + symbol: FMADD_S + name: FMADD_S + assembly_mnemonic: fmadd.s + encoding: 1487176771 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS3 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R4 + assembly_format: FRD_FRS1_FRS2_FRS3_RM + - + id: 1121 + symbol: FMSUB_S + name: FMSUB_S + assembly_mnemonic: fmsub.s + encoding: 1487176775 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS3 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R4 + assembly_format: FRD_FRS1_FRS2_FRS3_RM + - + id: 1122 + symbol: FNMSUB_S + name: FNMSUB_S + assembly_mnemonic: fnmsub.s + encoding: 1487176779 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS3 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R4 + assembly_format: FRD_FRS1_FRS2_FRS3_RM + - + id: 1123 + symbol: FNMADD_S + name: FNMADD_S + assembly_mnemonic: fnmadd.s + encoding: 1487176783 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS3 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R4 + assembly_format: FRD_FRS1_FRS2_FRS3_RM + - + id: 1124 + symbol: FADD_S + name: FADD_S + assembly_mnemonic: fadd.s + encoding: 10781779 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2_RM + - + id: 1125 + symbol: FSUB_S + name: FSUB_S + assembly_mnemonic: fsub.s + encoding: 144999507 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2_RM + - + id: 1126 + symbol: FMUL_S + name: FMUL_S + assembly_mnemonic: fmul.s + encoding: 279217235 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_MUL + encoding_category: R + assembly_format: FRD_FRS1_FRS2_RM + - + id: 1127 + symbol: FDIV_S + name: FDIV_S + assembly_mnemonic: fdiv.s + encoding: 413434963 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_DIV + encoding_category: R + assembly_format: FRD_FRS1_FRS2_RM + - + id: 1128 + symbol: FSQRT_S + name: FSQRT_S + assembly_mnemonic: fsqrt.s + encoding: 1476691027 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_SQRT + encoding_category: R + assembly_format: FRD_FRS1_RM + - + id: 1129 + symbol: FSGNJ_S + name: FSGNJ_S + assembly_mnemonic: fsgnj.s + encoding: 547652691 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1130 + symbol: FSGNJN_S + name: FSGNJN_S + assembly_mnemonic: fsgnjn.s + encoding: 547656787 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1131 + symbol: FSGNJX_S + name: FSGNJX_S + assembly_mnemonic: fsgnjx.s + encoding: 547660883 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1132 + symbol: FMIN_S + name: FMIN_S + assembly_mnemonic: fmin.s + encoding: 681870419 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1133 + symbol: FMAX_S + name: FMAX_S + assembly_mnemonic: fmax.s + encoding: 681874515 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: FRD_FRS1_FRS2 + - + id: 1134 + symbol: FCVT_W_S + name: FCVT_W_S + assembly_mnemonic: fcvt.w.s + encoding: 3221521491 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1_RM + - + id: 1135 + symbol: FCVT_WU_S + name: FCVT_WU_S + assembly_mnemonic: fcvt.wu.s + encoding: 3222570067 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1_RM + - + id: 1136 + symbol: FCVT_L_S + name: FCVT_L_S + assembly_mnemonic: fcvt.l.s + encoding: 3223618643 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1_RM + - + id: 1137 + symbol: FCVT_LU_S + name: FCVT_LU_S + assembly_mnemonic: fcvt.lu.s + encoding: 3224667219 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1_RM + - + id: 1138 + symbol: FMV_X_W + name: FMV_X_W + assembly_mnemonic: fmv.x.w + encoding: 3758392403 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1 + - + id: 1139 + symbol: FEQ_S + name: FEQ_S + assembly_mnemonic: feq.s + encoding: 2695144531 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: RD_FRS1_FRS2 + - + id: 1140 + symbol: FLT_S + name: FLT_S + assembly_mnemonic: flt.s + encoding: 2695140435 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: RD_FRS1_FRS2 + - + id: 1141 + symbol: FLE_S + name: FLE_S + assembly_mnemonic: fle.s + encoding: 2695136339 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS2 } + num_explicit_defs: 1 + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_ADD + encoding_category: R + assembly_format: RD_FRS1_FRS2 + - + id: 1142 + symbol: FCLASS_S + name: FCLASS_S + assembly_mnemonic: fclass.s + encoding: 3758396499 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR, name: FRS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: RD_FRS1 + - + id: 1143 + symbol: FCVT_S_W + name: FCVT_S_W + assembly_mnemonic: fcvt.s.w + encoding: 3489956947 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1_RM + - + id: 1144 + symbol: FCVT_S_WU + name: FCVT_S_WU + assembly_mnemonic: fcvt.s.wu + encoding: 3491005523 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1_RM + - + id: 1145 + symbol: FCVT_S_L + name: FCVT_S_L + assembly_mnemonic: fcvt.s.l + encoding: 3492054099 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1_RM + - + id: 1146 + symbol: FCVT_S_LU + name: FCVT_S_LU + assembly_mnemonic: fcvt.s.lu + encoding: 3493102675 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: RM, name: RM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [may_raise_fp_exception, produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1_RM + - + id: 1147 + symbol: FMV_W_X + name: FMV_W_X + assembly_mnemonic: fmv.w.x + encoding: 4026827859 + operands: + - { kinds: [register], role: def, register_class: FPR32, register_bank: FPR, name: FRD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: FP_CONVERT + encoding_category: R + assembly_format: FRD_RS1 diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc new file mode 100644 index 0000000..3c5711c --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc @@ -0,0 +1,875 @@ +instructions: + - + id: 1024 + symbol: LUI + name: LUI + assembly_mnemonic: lui + encoding: 5175 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: UIMM20, allowed_target_flags: 32, name: IMM } + num_explicit_defs: 1 + flags: [produces_code, rematerializable] + scheduling_class: ALU + encoding_category: U + assembly_format: RD_IMM + - + id: 1025 + symbol: AUIPC + name: AUIPC + assembly_mnemonic: auipc + encoding: 5143 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [immediate, basic_block, global_symbol, external_symbol, mc_symbol], immediate_predicate: UIMM20, allowed_target_flags: 3, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: U + assembly_format: RD_IMM + - + id: 1026 + symbol: ADDI + name: ADDI + assembly_mnemonic: addi + encoding: 1344531 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 68, name: IMM } + num_explicit_defs: 1 + flags: [produces_code, rematerializable] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1042 + symbol: SRLI + name: SRLI + assembly_mnemonic: srli + encoding: 1365011 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1043 + symbol: SRAI + name: SRAI + assembly_mnemonic: srai + encoding: 1075106835 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1044 + symbol: ADDIW + name: ADDIW + assembly_mnemonic: addiw + encoding: 1344539 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + num_explicit_defs: 1 + flags: [produces_code, rematerializable] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1045 + symbol: SLLIW + name: SLLIW + assembly_mnemonic: slliw + encoding: 1348635 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: UIMM5, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1046 + symbol: SRLIW + name: SRLIW + assembly_mnemonic: srliw + encoding: 1365019 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: UIMM5, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1047 + symbol: SRAIW + name: SRAIW + assembly_mnemonic: sraiw + encoding: 1075106843 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: UIMM5, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1048 + symbol: SLL + name: SLL + assembly_mnemonic: sll + encoding: 10785843 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1049 + symbol: SLT + name: SLT + assembly_mnemonic: slt + encoding: 10789939 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1050 + symbol: SLTU + name: SLTU + assembly_mnemonic: sltu + encoding: 10794035 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1051 + symbol: XOR + name: XOR + assembly_mnemonic: xor + encoding: 10798131 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1052 + symbol: SRL + name: SRL + assembly_mnemonic: srl + encoding: 10802227 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1053 + symbol: SRA + name: SRA + assembly_mnemonic: sra + encoding: 1084544051 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1054 + symbol: OR + name: OR + assembly_mnemonic: or + encoding: 10806323 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1055 + symbol: AND + name: AND + assembly_mnemonic: and + encoding: 10810419 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1056 + symbol: ADDW + name: ADDW + assembly_mnemonic: addw + encoding: 10781755 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1057 + symbol: SUBW + name: SUBW + assembly_mnemonic: subw + encoding: 1084523579 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1058 + symbol: SLLW + name: SLLW + assembly_mnemonic: sllw + encoding: 10785851 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1059 + symbol: SRLW + name: SRLW + assembly_mnemonic: srlw + encoding: 10802235 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1060 + symbol: SRAW + name: SRAW + assembly_mnemonic: sraw + encoding: 1084544059 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1061 + symbol: LB + name: LB + assembly_mnemonic: lb + encoding: 8684547 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: I + assembly_format: RD_OFFSET_RS1 + - + id: 1062 + symbol: LH + name: LH + assembly_mnemonic: lh + encoding: 8688643 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: I + assembly_format: RD_OFFSET_RS1 + - + id: 1063 + symbol: LW + name: LW + assembly_mnemonic: lw + encoding: 8692739 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: I + assembly_format: RD_OFFSET_RS1 + - + id: 1064 + symbol: LBU + name: LBU + assembly_mnemonic: lbu + encoding: 8700931 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: I + assembly_format: RD_OFFSET_RS1 + - + id: 1065 + symbol: LHU + name: LHU + assembly_mnemonic: lhu + encoding: 8705027 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: I + assembly_format: RD_OFFSET_RS1 + - + id: 1066 + symbol: LWU + name: LWU + assembly_mnemonic: lwu + encoding: 8709123 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: I + assembly_format: RD_OFFSET_RS1 + - + id: 1067 + symbol: SB + name: SB + assembly_mnemonic: sb + encoding: 10781731 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 0 + flags: [may_store, produces_code] + scheduling_class: STORE + encoding_category: S + assembly_format: RS2_OFFSET_RS1 + - + id: 1068 + symbol: SH + name: SH + assembly_mnemonic: sh + encoding: 10785827 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 0 + flags: [may_store, produces_code] + scheduling_class: STORE + encoding_category: S + assembly_format: RS2_OFFSET_RS1 + - + id: 1069 + symbol: SW + name: SW + assembly_mnemonic: sw + encoding: 10789923 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 0 + flags: [may_store, produces_code] + scheduling_class: STORE + encoding_category: S + assembly_format: RS2_OFFSET_RS1 + - + id: 1070 + symbol: BLT + name: BLT + assembly_mnemonic: blt + encoding: 9715811 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [terminator, branch, produces_code] + scheduling_class: BRANCH + encoding_category: B + assembly_format: RS1_RS2_TARGET + - + id: 1071 + symbol: BGE + name: BGE + assembly_mnemonic: bge + encoding: 9719907 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [terminator, branch, produces_code] + scheduling_class: BRANCH + encoding_category: B + assembly_format: RS1_RS2_TARGET + - + id: 1072 + symbol: BLTU + name: BLTU + assembly_mnemonic: bltu + encoding: 9724003 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [terminator, branch, produces_code] + scheduling_class: BRANCH + encoding_category: B + assembly_format: RS1_RS2_TARGET + - + id: 1073 + symbol: BGEU + name: BGEU + assembly_mnemonic: bgeu + encoding: 9728099 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [terminator, branch, produces_code] + scheduling_class: BRANCH + encoding_category: B + assembly_format: RS1_RS2_TARGET + - + id: 1074 + symbol: JALR + name: JALR + assembly_mnemonic: jalr + encoding: 1344615 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate, basic_block, global_symbol, external_symbol, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 4, name: IMM } + num_explicit_defs: 1 + flags: [terminator, branch, indirect_branch, produces_code] + scheduling_class: BRANCH + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1075 + symbol: FENCE + name: FENCE + assembly_mnemonic: fence + encoding: 15 + operands: + - { kinds: [immediate], immediate_predicate: UIMM4, name: PRED } + - { kinds: [immediate], immediate_predicate: UIMM4, name: SUCC } + num_explicit_defs: 0 + flags: [has_side_effects, produces_code] + scheduling_class: FENCE + encoding_category: I + assembly_format: IMM_IMM + - + id: 1076 + symbol: FENCE_I + name: FENCE_I + assembly_mnemonic: fence.i + encoding: 4111 + operands: [] + num_explicit_defs: 0 + flags: [has_side_effects, produces_code] + scheduling_class: FENCE + encoding_category: I + assembly_format: NONE + - + id: 1077 + symbol: CSRRW + name: CSRRW + assembly_mnemonic: csrrw + encoding: 1348723 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [has_side_effects, produces_code] + scheduling_class: SYSTEM + encoding_category: SYSTEM + assembly_format: RD_CSR_RS1 + - + id: 1078 + symbol: CSRRS + name: CSRRS + assembly_mnemonic: csrrs + encoding: 1352819 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [has_side_effects, produces_code] + scheduling_class: SYSTEM + encoding_category: SYSTEM + assembly_format: RD_CSR_RS1 + - + id: 1079 + symbol: CSRRC + name: CSRRC + assembly_mnemonic: csrrc + encoding: 1356915 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + num_explicit_defs: 1 + flags: [has_side_effects, produces_code] + scheduling_class: SYSTEM + encoding_category: SYSTEM + assembly_format: RD_CSR_RS1 + - + id: 1080 + symbol: CSRRWI + name: CSRRWI + assembly_mnemonic: csrrwi + encoding: 1102963 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } + - { kinds: [immediate], immediate_predicate: UIMM5, name: ZIMM } + num_explicit_defs: 1 + flags: [has_side_effects, produces_code] + scheduling_class: SYSTEM + encoding_category: SYSTEM + assembly_format: RD_CSR_IMM + - + id: 1081 + symbol: CSRRSI + name: CSRRSI + assembly_mnemonic: csrrsi + encoding: 1107059 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } + - { kinds: [immediate], immediate_predicate: UIMM5, name: ZIMM } + num_explicit_defs: 1 + flags: [has_side_effects, produces_code] + scheduling_class: SYSTEM + encoding_category: SYSTEM + assembly_format: RD_CSR_IMM + - + id: 1082 + symbol: CSRRCI + name: CSRRCI + assembly_mnemonic: csrrci + encoding: 1111155 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [immediate], immediate_predicate: UIMM12, name: CSR } + - { kinds: [immediate], immediate_predicate: UIMM5, name: ZIMM } + num_explicit_defs: 1 + flags: [has_side_effects, produces_code] + scheduling_class: SYSTEM + encoding_category: SYSTEM + assembly_format: RD_CSR_IMM + - + id: 1027 + symbol: ADD + name: ADD + assembly_mnemonic: add + encoding: 10781747 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1028 + symbol: SUB + name: SUB + assembly_mnemonic: sub + encoding: 1084523571 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1029 + symbol: LD + name: LD + assembly_mnemonic: ld + encoding: 8696835 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, memory_role: value, name: RD } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 1 + flags: [may_load, produces_code] + scheduling_class: LOAD + encoding_category: I + assembly_format: RD_OFFSET_RS1 + - + id: 1030 + symbol: SD + name: SD + assembly_mnemonic: sd + encoding: 10794019 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, memory_role: value, name: RS2 } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, memory_role: address, name: RS1 } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, name: IMM, allowed_target_flags: 68 } + num_explicit_defs: 0 + flags: [may_store, produces_code] + scheduling_class: STORE + encoding_category: S + assembly_format: RS2_OFFSET_RS1 + - + id: 1031 + symbol: BEQ + name: BEQ + assembly_mnemonic: beq + encoding: 9699427 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [terminator, branch, produces_code] + scheduling_class: BRANCH + encoding_category: B + assembly_format: RS1_RS2_TARGET + - + id: 1032 + symbol: BNE + name: BNE + assembly_mnemonic: bne + encoding: 9703523 + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [terminator, branch, produces_code] + scheduling_class: BRANCH + encoding_category: B + assembly_format: RS1_RS2_TARGET + - + id: 1033 + symbol: JAL + name: JAL + assembly_mnemonic: jal + encoding: 1135 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 1 + flags: [terminator, branch, produces_code] + scheduling_class: BRANCH + encoding_category: J + assembly_format: RD_TARGET + - + id: 1034 + symbol: ECALL + name: ECALL + assembly_mnemonic: ecall + encoding: 115 + operands: [] + num_explicit_defs: 0 + flags: [has_side_effects, produces_code] + scheduling_class: SYSTEM + encoding_category: SYSTEM + assembly_format: NONE + - + id: 1035 + symbol: EBREAK + name: EBREAK + assembly_mnemonic: ebreak + encoding: 1048691 + operands: [] + num_explicit_defs: 0 + flags: [has_side_effects, produces_code] + scheduling_class: SYSTEM + encoding_category: SYSTEM + assembly_format: NONE + - + id: 1036 + symbol: SLTI + name: SLTI + assembly_mnemonic: slti + encoding: 1352723 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1037 + symbol: SLTIU + name: SLTIU + assembly_mnemonic: sltiu + encoding: 1356819 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1038 + symbol: XORI + name: XORI + assembly_mnemonic: xori + encoding: 1360915 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1039 + symbol: ORI + name: ORI + assembly_mnemonic: ori + encoding: 1369107 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1040 + symbol: ANDI + name: ANDI + assembly_mnemonic: andi + encoding: 1373203 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1041 + symbol: SLLI + name: SLLI + assembly_mnemonic: slli + encoding: 1348627 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoM.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoM.rccdesc new file mode 100644 index 0000000..62e8e6c --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoM.rccdesc @@ -0,0 +1,196 @@ +instructions: + - + id: 1083 + symbol: MUL + name: MUL + assembly_mnemonic: mul + encoding: 44336179 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code, commutable] + scheduling_class: MUL + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1084 + symbol: MULH + name: MULH + assembly_mnemonic: mulh + encoding: 44340275 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code, commutable] + scheduling_class: MUL + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1085 + symbol: MULHSU + name: MULHSU + assembly_mnemonic: mulhsu + encoding: 44344371 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: MUL + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1086 + symbol: MULHU + name: MULHU + assembly_mnemonic: mulhu + encoding: 44348467 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code, commutable] + scheduling_class: MUL + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1087 + symbol: DIV + name: DIV + assembly_mnemonic: div + encoding: 44352563 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: DIV + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1088 + symbol: DIVU + name: DIVU + assembly_mnemonic: divu + encoding: 44356659 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: DIV + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1089 + symbol: REM + name: REM + assembly_mnemonic: rem + encoding: 44360755 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: DIV + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1090 + symbol: REMU + name: REMU + assembly_mnemonic: remu + encoding: 44364851 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: DIV + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1091 + symbol: MULW + name: MULW + assembly_mnemonic: mulw + encoding: 44336187 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code, commutable] + scheduling_class: MUL + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1092 + symbol: DIVW + name: DIVW + assembly_mnemonic: divw + encoding: 44352571 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: DIV + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1093 + symbol: DIVUW + name: DIVUW + assembly_mnemonic: divuw + encoding: 44356667 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: DIV + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1094 + symbol: REMW + name: REMW + assembly_mnemonic: remw + encoding: 44360763 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: DIV + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1095 + symbol: REMUW + name: REMUW + assembly_mnemonic: remuw + encoding: 44364859 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: DIV + encoding_category: R + assembly_format: RD_RS1_RS2 diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc new file mode 100644 index 0000000..4f16ec6 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc @@ -0,0 +1,380 @@ +instructions: + - + id: 1229 + symbol: G_SLLW + name: G_SLLW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1230 + symbol: G_SRAW + name: G_SRAW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1231 + symbol: G_DIVW + name: G_DIVW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1232 + symbol: G_CLZW + name: G_CLZW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1233 + symbol: G_CTZW + name: G_CTZW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1234 + symbol: G_FCVT_W_RV64 + name: G_FCVT_W_RV64 + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 1 } + - { kinds: [immediate] } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1235 + symbol: G_FCLASS + name: G_FCLASS + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 1 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1236 + symbol: G_ROLW + name: G_ROLW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1237 + symbol: G_SRLW + name: G_SRLW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1238 + symbol: G_DIVUW + name: G_DIVUW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1239 + symbol: G_REMUW + name: G_REMUW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1240 + symbol: G_RORW + name: G_RORW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1241 + symbol: G_BREV8 + name: G_BREV8 + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1242 + symbol: G_FCVT_WU_RV64 + name: G_FCVT_WU_RV64 + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 1 } + - { kinds: [immediate] } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1243 + symbol: G_CLSW + name: G_CLSW + operands: + - { kinds: [register], role: def, type_index: 0 } + - { kinds: [register], role: use, type_index: 0 } + num_explicit_defs: 1 + flags: [generic, pseudo, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1244 + symbol: Select_GPR_Using_CC_GPR + name: Select_GPR_Using_CC_GPR + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } + - { kinds: [immediate] } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } + num_explicit_defs: 1 + flags: [pseudo, produces_code, allowed_pre_legalizer] + owner: instruction_select + deadline: selected + - + id: 1245 + symbol: ReadFFLAGS + name: ReadFFLAGS + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR } + num_explicit_defs: 1 + implicit_uses: [{ register: FFLAGS }] + flags: [pseudo, produces_code, allowed_pre_legalizer, has_side_effects] + owner: post_ra_expansion + deadline: post_ra_finalized + + - + id: 1246 + symbol: WriteFFLAGS + name: WriteFFLAGS + operands: + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } + num_explicit_defs: 0 + implicit_defs: [{ register: FFLAGS }] + flags: [pseudo, produces_code, allowed_pre_legalizer, has_side_effects] + owner: post_ra_expansion + deadline: post_ra_finalized + - + id: 1217 + symbol: PseudoLOAD_STACK_ARG + name: PseudoLOAD_STACK_ARG + operands: + - { kinds: [register], role: def, memory_role: value } + - { kinds: [frame_index] } + - { kinds: [immediate, integer_immediate] } + - { kinds: [immediate] } + num_explicit_defs: 1 + flags: [pseudo, produces_code, allowed_pre_legalizer, may_load] + owner: instruction_select + deadline: selected + - + id: 1218 + symbol: PseudoSTORE_STACK_ARG + name: PseudoSTORE_STACK_ARG + operands: + - { kinds: [register], role: use, memory_role: value } + - { kinds: [frame_index] } + - { kinds: [immediate, integer_immediate] } + - { kinds: [immediate] } + num_explicit_defs: 0 + flags: [pseudo, produces_code, allowed_pre_legalizer, may_store] + owner: instruction_select + deadline: selected + - + id: 1219 + symbol: PseudoBYVAL_COPY + name: PseudoBYVAL_COPY + operands: + - { kinds: [register], role: def } + - { kinds: [register], role: use, memory_role: address } + - { kinds: [frame_index] } + - { kinds: [immediate, integer_immediate] } + - { kinds: [immediate, integer_immediate] } + num_explicit_defs: 1 + flags: [pseudo, produces_code, allowed_pre_legalizer, may_load, may_store] + owner: instruction_select + deadline: selected + - + id: 1220 + symbol: ADJCALLSTACKDOWN + name: ADJCALLSTACKDOWN + operands: + - { kinds: [immediate, integer_immediate] } + - { kinds: [immediate, integer_immediate] } + num_explicit_defs: 0 + implicit_defs: [{ register: X2 }] + implicit_uses: [{ register: X2 }] + flags: [pseudo, allowed_pre_legalizer, has_side_effects] + owner: prologue_epilogue_insertion + deadline: frame_finalized + - + id: 1221 + symbol: ADJCALLSTACKUP + name: ADJCALLSTACKUP + operands: + - { kinds: [immediate, integer_immediate] } + - { kinds: [immediate, integer_immediate] } + num_explicit_defs: 0 + implicit_defs: [{ register: X2 }] + implicit_uses: [{ register: X2 }] + flags: [pseudo, allowed_pre_legalizer, has_side_effects] + owner: prologue_epilogue_insertion + deadline: frame_finalized + - + id: 1222 + symbol: PseudoCALL + name: PseudoCALL + operands: + - { kinds: [global_symbol, external_symbol, register], role: use, allowed_target_flags: 1 } + - { kinds: [register_mask], optional: true } + num_explicit_defs: 0 + implicit_defs: [{ register: X1 }] + allow_extra_implicit_operands: true + flags: [pseudo, produces_code, allowed_pre_legalizer, call, may_load, may_store, has_side_effects, not_duplicable, unmodeled_side_effects] + size: 8 + owner: post_ra_expansion + deadline: post_ra_finalized + - + id: 1223 + symbol: PseudoTAIL + name: PseudoTAIL + operands: + - { kinds: [global_symbol, external_symbol, register], role: use, allowed_target_flags: 1 } + - { kinds: [register_mask], optional: true } + num_explicit_defs: 0 + allow_extra_implicit_operands: true + flags: [pseudo, produces_code, allowed_pre_legalizer, terminator, branch, call, barrier, may_load, may_store, has_side_effects, not_duplicable, unmodeled_side_effects] + size: 8 + owner: post_ra_expansion + deadline: post_ra_finalized + - + id: 1224 + symbol: PseudoRET + name: PseudoRET + operands: [] + num_explicit_defs: 0 + allow_extra_implicit_operands: true + flags: [pseudo, produces_code, allowed_pre_legalizer, terminator, return, barrier] + size: 4 + owner: post_ra_expansion + deadline: post_ra_finalized + + - + id: 1225 + symbol: JALR_CALL + name: JALR_CALL + assembly_mnemonic: jalr + encoding: 1344615 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 4, name: IMM } + - { kinds: [register_mask] } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [call, may_load, may_store, has_side_effects, produces_code, not_duplicable, unmodeled_side_effects] + scheduling_class: BRANCH + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1226 + symbol: JALR_TAIL + name: JALR_TAIL + assembly_mnemonic: jalr + encoding: 1344615 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 4, name: IMM } + - { kinds: [register_mask] } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [terminator, branch, indirect_branch, call, barrier, may_load, may_store, has_side_effects, produces_code, not_duplicable, unmodeled_side_effects] + scheduling_class: BRANCH + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1227 + symbol: JALR_RET + name: JALR_RET + assembly_mnemonic: jalr + encoding: 1344615 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [terminator, return, barrier, produces_code] + scheduling_class: BRANCH + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1228 + symbol: PseudoBR + name: PseudoBR + operands: + - { kinds: [basic_block], name: TARGET } + num_explicit_defs: 0 + flags: [pseudo, produces_code, allowed_pre_legalizer, terminator, branch, barrier] + size: 4 + owner: post_ra_expansion + deadline: post_ra_finalized diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoZb.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoZb.rccdesc new file mode 100644 index 0000000..103c3ab --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoZb.rccdesc @@ -0,0 +1,237 @@ +instructions: + - + id: 1247 + symbol: SH1ADD + name: SH1ADD + assembly_mnemonic: sh1add + encoding: 547660851 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1248 + symbol: SH2ADD + name: SH2ADD + assembly_mnemonic: sh2add + encoding: 547669043 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1249 + symbol: SH3ADD + name: SH3ADD + assembly_mnemonic: sh3add + encoding: 547677235 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1250 + symbol: SH1ADD_UW + name: SH1ADD_UW + assembly_mnemonic: sh1add.uw + encoding: 547660859 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1251 + symbol: SH2ADD_UW + name: SH2ADD_UW + assembly_mnemonic: sh2add.uw + encoding: 547669051 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1252 + symbol: SH3ADD_UW + name: SH3ADD_UW + assembly_mnemonic: sh3add.uw + encoding: 547677243 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1253 + symbol: SLLI_UW + name: SLLI_UW + assembly_mnemonic: slli.uw + encoding: 135566363 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [immediate], immediate_predicate: UIMM6, name: IMM } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1_IMM + - + id: 1254 + symbol: ADD_UW + name: ADD_UW + assembly_mnemonic: add.uw + encoding: 144999483 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1255 + symbol: SEXT_B + name: SEXT_B + assembly_mnemonic: sext.b + encoding: 1615107091 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1 + - + id: 1256 + symbol: SEXT_H + name: SEXT_H + assembly_mnemonic: sext.h + encoding: 1616155667 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: I + assembly_format: RD_RS1 + - + id: 1257 + symbol: ZEXT_H_RV32 + name: ZEXT_H_RV32 + assembly_mnemonic: zext.h + encoding: 134530099 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1 + - + id: 1258 + symbol: ZEXT_H_RV64 + name: ZEXT_H_RV64 + assembly_mnemonic: zext.h + encoding: 134530107 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + num_explicit_defs: 1 + flags: [produces_code] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1 + - + id: 1259 + symbol: MIN + name: MIN + assembly_mnemonic: min + encoding: 178570291 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code, commutable] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1260 + symbol: MINU + name: MINU + assembly_mnemonic: minu + encoding: 178574387 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code, commutable] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1261 + symbol: MAX + name: MAX + assembly_mnemonic: max + encoding: 178578483 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code, commutable] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 + - + id: 1262 + symbol: MAXU + name: MAXU + assembly_mnemonic: maxu + encoding: 178582579 + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } + num_explicit_defs: 1 + flags: [produces_code, commutable] + scheduling_class: ALU + encoding_category: R + assembly_format: RD_RS1_RS2 diff --git a/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc new file mode 100644 index 0000000..7a63dc0 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc @@ -0,0 +1,383 @@ +register_units: + - { id: 1, symbol: U_X0, name: x0.unit } + - { id: 2, symbol: U_X1, name: x1.unit } + - { id: 3, symbol: U_X2, name: x2.unit } + - { id: 4, symbol: U_X3, name: x3.unit } + - { id: 5, symbol: U_X4, name: x4.unit } + - { id: 6, symbol: U_X5, name: x5.unit } + - { id: 7, symbol: U_X6, name: x6.unit } + - { id: 8, symbol: U_X7, name: x7.unit } + - { id: 9, symbol: U_X8, name: x8.unit } + - { id: 10, symbol: U_X9, name: x9.unit } + - { id: 11, symbol: U_X10, name: x10.unit } + - { id: 12, symbol: U_X11, name: x11.unit } + - { id: 13, symbol: U_X12, name: x12.unit } + - { id: 14, symbol: U_X13, name: x13.unit } + - { id: 15, symbol: U_X14, name: x14.unit } + - { id: 16, symbol: U_X15, name: x15.unit } + - { id: 17, symbol: U_X16, name: x16.unit } + - { id: 18, symbol: U_X17, name: x17.unit } + - { id: 19, symbol: U_X18, name: x18.unit } + - { id: 20, symbol: U_X19, name: x19.unit } + - { id: 21, symbol: U_X20, name: x20.unit } + - { id: 22, symbol: U_X21, name: x21.unit } + - { id: 23, symbol: U_X22, name: x22.unit } + - { id: 24, symbol: U_X23, name: x23.unit } + - { id: 25, symbol: U_X24, name: x24.unit } + - { id: 26, symbol: U_X25, name: x25.unit } + - { id: 27, symbol: U_X26, name: x26.unit } + - { id: 28, symbol: U_X27, name: x27.unit } + - { id: 29, symbol: U_X28, name: x28.unit } + - { id: 30, symbol: U_X29, name: x29.unit } + - { id: 31, symbol: U_X30, name: x30.unit } + - { id: 32, symbol: U_X31, name: x31.unit } + - { id: 33, symbol: U_F0, name: f0.unit } + - { id: 34, symbol: U_F1, name: f1.unit } + - { id: 35, symbol: U_F2, name: f2.unit } + - { id: 36, symbol: U_F3, name: f3.unit } + - { id: 37, symbol: U_F4, name: f4.unit } + - { id: 38, symbol: U_F5, name: f5.unit } + - { id: 39, symbol: U_F6, name: f6.unit } + - { id: 40, symbol: U_F7, name: f7.unit } + - { id: 41, symbol: U_F8, name: f8.unit } + - { id: 42, symbol: U_F9, name: f9.unit } + - { id: 43, symbol: U_F10, name: f10.unit } + - { id: 44, symbol: U_F11, name: f11.unit } + - { id: 45, symbol: U_F12, name: f12.unit } + - { id: 46, symbol: U_F13, name: f13.unit } + - { id: 47, symbol: U_F14, name: f14.unit } + - { id: 48, symbol: U_F15, name: f15.unit } + - { id: 49, symbol: U_F16, name: f16.unit } + - { id: 50, symbol: U_F17, name: f17.unit } + - { id: 51, symbol: U_F18, name: f18.unit } + - { id: 52, symbol: U_F19, name: f19.unit } + - { id: 53, symbol: U_F20, name: f20.unit } + - { id: 54, symbol: U_F21, name: f21.unit } + - { id: 55, symbol: U_F22, name: f22.unit } + - { id: 56, symbol: U_F23, name: f23.unit } + - { id: 57, symbol: U_F24, name: f24.unit } + - { id: 58, symbol: U_F25, name: f25.unit } + - { id: 59, symbol: U_F26, name: f26.unit } + - { id: 60, symbol: U_F27, name: f27.unit } + - { id: 61, symbol: U_F28, name: f28.unit } + - { id: 62, symbol: U_F29, name: f29.unit } + - { id: 63, symbol: U_F30, name: f30.unit } + - { id: 64, symbol: U_F31, name: f31.unit } + - { id: 65, symbol: U_FFLAGS, name: fflags.unit } + - { id: 66, symbol: U_FRM, name: frm.unit } + - { id: 67, symbol: U_V0, name: v0.unit } + - { id: 68, symbol: U_V1, name: v1.unit } + - { id: 69, symbol: U_V2, name: v2.unit } + - { id: 70, symbol: U_V3, name: v3.unit } + - { id: 71, symbol: U_V4, name: v4.unit } + - { id: 72, symbol: U_V5, name: v5.unit } + - { id: 73, symbol: U_V6, name: v6.unit } + - { id: 74, symbol: U_V7, name: v7.unit } + - { id: 75, symbol: U_V8, name: v8.unit } + - { id: 76, symbol: U_V9, name: v9.unit } + - { id: 77, symbol: U_V10, name: v10.unit } + - { id: 78, symbol: U_V11, name: v11.unit } + - { id: 79, symbol: U_V12, name: v12.unit } + - { id: 80, symbol: U_V13, name: v13.unit } + - { id: 81, symbol: U_V14, name: v14.unit } + - { id: 82, symbol: U_V15, name: v15.unit } + - { id: 83, symbol: U_V16, name: v16.unit } + - { id: 84, symbol: U_V17, name: v17.unit } + - { id: 85, symbol: U_V18, name: v18.unit } + - { id: 86, symbol: U_V19, name: v19.unit } + - { id: 87, symbol: U_V20, name: v20.unit } + - { id: 88, symbol: U_V21, name: v21.unit } + - { id: 89, symbol: U_V22, name: v22.unit } + - { id: 90, symbol: U_V23, name: v23.unit } + - { id: 91, symbol: U_V24, name: v24.unit } + - { id: 92, symbol: U_V25, name: v25.unit } + - { id: 93, symbol: U_V26, name: v26.unit } + - { id: 94, symbol: U_V27, name: v27.unit } + - { id: 95, symbol: U_V28, name: v28.unit } + - { id: 96, symbol: U_V29, name: v29.unit } + - { id: 97, symbol: U_V30, name: v30.unit } + - { id: 98, symbol: U_V31, name: v31.unit } + +registers: + - { id: 1, symbol: X0, name: x0, encoding: 0, dwarf_register: 0, units: [{ unit: U_X0, lanes: 1 }], constant: true, reserved: true, aliases: [zero] } + - { id: 2, symbol: X1, name: x1, encoding: 1, dwarf_register: 1, units: [{ unit: U_X1, lanes: 1 }], aliases: [ra] } + - { id: 3, symbol: X2, name: x2, encoding: 2, dwarf_register: 2, units: [{ unit: U_X2, lanes: 1 }], reserved: true, aliases: [sp] } + - { id: 4, symbol: X3, name: x3, encoding: 3, dwarf_register: 3, units: [{ unit: U_X3, lanes: 1 }], reserved: true, aliases: [gp] } + - { id: 5, symbol: X4, name: x4, encoding: 4, dwarf_register: 4, units: [{ unit: U_X4, lanes: 1 }], reserved: true, aliases: [tp] } + - { id: 6, symbol: X5, name: x5, encoding: 5, dwarf_register: 5, units: [{ unit: U_X5, lanes: 1 }], aliases: [t0] } + - { id: 7, symbol: X6, name: x6, encoding: 6, dwarf_register: 6, units: [{ unit: U_X6, lanes: 1 }], aliases: [t1] } + - { id: 8, symbol: X7, name: x7, encoding: 7, dwarf_register: 7, units: [{ unit: U_X7, lanes: 1 }], aliases: [t2] } + - { id: 9, symbol: X8, name: x8, encoding: 8, dwarf_register: 8, units: [{ unit: U_X8, lanes: 1 }], aliases: [s0, fp] } + - { id: 10, symbol: X9, name: x9, encoding: 9, dwarf_register: 9, units: [{ unit: U_X9, lanes: 1 }], aliases: [s1] } + - { id: 11, symbol: X10, name: x10, encoding: 10, dwarf_register: 10, units: [{ unit: U_X10, lanes: 1 }], aliases: [a0] } + - { id: 12, symbol: X11, name: x11, encoding: 11, dwarf_register: 11, units: [{ unit: U_X11, lanes: 1 }], aliases: [a1] } + - { id: 13, symbol: X12, name: x12, encoding: 12, dwarf_register: 12, units: [{ unit: U_X12, lanes: 1 }], aliases: [a2] } + - { id: 14, symbol: X13, name: x13, encoding: 13, dwarf_register: 13, units: [{ unit: U_X13, lanes: 1 }], aliases: [a3] } + - { id: 15, symbol: X14, name: x14, encoding: 14, dwarf_register: 14, units: [{ unit: U_X14, lanes: 1 }], aliases: [a4] } + - { id: 16, symbol: X15, name: x15, encoding: 15, dwarf_register: 15, units: [{ unit: U_X15, lanes: 1 }], aliases: [a5] } + - { id: 17, symbol: X16, name: x16, encoding: 16, dwarf_register: 16, units: [{ unit: U_X16, lanes: 1 }], aliases: [a6] } + - { id: 18, symbol: X17, name: x17, encoding: 17, dwarf_register: 17, units: [{ unit: U_X17, lanes: 1 }], aliases: [a7] } + - { id: 19, symbol: X18, name: x18, encoding: 18, dwarf_register: 18, units: [{ unit: U_X18, lanes: 1 }], aliases: [s2] } + - { id: 20, symbol: X19, name: x19, encoding: 19, dwarf_register: 19, units: [{ unit: U_X19, lanes: 1 }], aliases: [s3] } + - { id: 21, symbol: X20, name: x20, encoding: 20, dwarf_register: 20, units: [{ unit: U_X20, lanes: 1 }], aliases: [s4] } + - { id: 22, symbol: X21, name: x21, encoding: 21, dwarf_register: 21, units: [{ unit: U_X21, lanes: 1 }], aliases: [s5] } + - { id: 23, symbol: X22, name: x22, encoding: 22, dwarf_register: 22, units: [{ unit: U_X22, lanes: 1 }], aliases: [s6] } + - { id: 24, symbol: X23, name: x23, encoding: 23, dwarf_register: 23, units: [{ unit: U_X23, lanes: 1 }], aliases: [s7] } + - { id: 25, symbol: X24, name: x24, encoding: 24, dwarf_register: 24, units: [{ unit: U_X24, lanes: 1 }], aliases: [s8] } + - { id: 26, symbol: X25, name: x25, encoding: 25, dwarf_register: 25, units: [{ unit: U_X25, lanes: 1 }], aliases: [s9] } + - { id: 27, symbol: X26, name: x26, encoding: 26, dwarf_register: 26, units: [{ unit: U_X26, lanes: 1 }], aliases: [s10] } + - { id: 28, symbol: X27, name: x27, encoding: 27, dwarf_register: 27, units: [{ unit: U_X27, lanes: 1 }], aliases: [s11] } + - { id: 29, symbol: X28, name: x28, encoding: 28, dwarf_register: 28, units: [{ unit: U_X28, lanes: 1 }], aliases: [t3] } + - { id: 30, symbol: X29, name: x29, encoding: 29, dwarf_register: 29, units: [{ unit: U_X29, lanes: 1 }], aliases: [t4] } + - { id: 31, symbol: X30, name: x30, encoding: 30, dwarf_register: 30, units: [{ unit: U_X30, lanes: 1 }], aliases: [t5] } + - { id: 32, symbol: X31, name: x31, encoding: 31, dwarf_register: 31, units: [{ unit: U_X31, lanes: 1 }], aliases: [t6] } + - { id: 33, symbol: F0_D, name: f0_d, encoding: 0, dwarf_register: 32, units: [{ unit: U_F0, lanes: 1 }], aliases: [ft0] } + - { id: 34, symbol: F1_D, name: f1_d, encoding: 1, dwarf_register: 33, units: [{ unit: U_F1, lanes: 1 }], aliases: [ft1] } + - { id: 35, symbol: F2_D, name: f2_d, encoding: 2, dwarf_register: 34, units: [{ unit: U_F2, lanes: 1 }], aliases: [ft2] } + - { id: 36, symbol: F3_D, name: f3_d, encoding: 3, dwarf_register: 35, units: [{ unit: U_F3, lanes: 1 }], aliases: [ft3] } + - { id: 37, symbol: F4_D, name: f4_d, encoding: 4, dwarf_register: 36, units: [{ unit: U_F4, lanes: 1 }], aliases: [ft4] } + - { id: 38, symbol: F5_D, name: f5_d, encoding: 5, dwarf_register: 37, units: [{ unit: U_F5, lanes: 1 }], aliases: [ft5] } + - { id: 39, symbol: F6_D, name: f6_d, encoding: 6, dwarf_register: 38, units: [{ unit: U_F6, lanes: 1 }], aliases: [ft6] } + - { id: 40, symbol: F7_D, name: f7_d, encoding: 7, dwarf_register: 39, units: [{ unit: U_F7, lanes: 1 }], aliases: [ft7] } + - { id: 41, symbol: F8_D, name: f8_d, encoding: 8, dwarf_register: 40, units: [{ unit: U_F8, lanes: 1 }], aliases: [fs0] } + - { id: 42, symbol: F9_D, name: f9_d, encoding: 9, dwarf_register: 41, units: [{ unit: U_F9, lanes: 1 }], aliases: [fs1] } + - { id: 43, symbol: F10_D, name: f10_d, encoding: 10, dwarf_register: 42, units: [{ unit: U_F10, lanes: 1 }], aliases: [fa0] } + - { id: 44, symbol: F11_D, name: f11_d, encoding: 11, dwarf_register: 43, units: [{ unit: U_F11, lanes: 1 }], aliases: [fa1] } + - { id: 45, symbol: F12_D, name: f12_d, encoding: 12, dwarf_register: 44, units: [{ unit: U_F12, lanes: 1 }], aliases: [fa2] } + - { id: 46, symbol: F13_D, name: f13_d, encoding: 13, dwarf_register: 45, units: [{ unit: U_F13, lanes: 1 }], aliases: [fa3] } + - { id: 47, symbol: F14_D, name: f14_d, encoding: 14, dwarf_register: 46, units: [{ unit: U_F14, lanes: 1 }], aliases: [fa4] } + - { id: 48, symbol: F15_D, name: f15_d, encoding: 15, dwarf_register: 47, units: [{ unit: U_F15, lanes: 1 }], aliases: [fa5] } + - { id: 49, symbol: F16_D, name: f16_d, encoding: 16, dwarf_register: 48, units: [{ unit: U_F16, lanes: 1 }], aliases: [fa6] } + - { id: 50, symbol: F17_D, name: f17_d, encoding: 17, dwarf_register: 49, units: [{ unit: U_F17, lanes: 1 }], aliases: [fa7] } + - { id: 51, symbol: F18_D, name: f18_d, encoding: 18, dwarf_register: 50, units: [{ unit: U_F18, lanes: 1 }], aliases: [fs2] } + - { id: 52, symbol: F19_D, name: f19_d, encoding: 19, dwarf_register: 51, units: [{ unit: U_F19, lanes: 1 }], aliases: [fs3] } + - { id: 53, symbol: F20_D, name: f20_d, encoding: 20, dwarf_register: 52, units: [{ unit: U_F20, lanes: 1 }], aliases: [fs4] } + - { id: 54, symbol: F21_D, name: f21_d, encoding: 21, dwarf_register: 53, units: [{ unit: U_F21, lanes: 1 }], aliases: [fs5] } + - { id: 55, symbol: F22_D, name: f22_d, encoding: 22, dwarf_register: 54, units: [{ unit: U_F22, lanes: 1 }], aliases: [fs6] } + - { id: 56, symbol: F23_D, name: f23_d, encoding: 23, dwarf_register: 55, units: [{ unit: U_F23, lanes: 1 }], aliases: [fs7] } + - { id: 57, symbol: F24_D, name: f24_d, encoding: 24, dwarf_register: 56, units: [{ unit: U_F24, lanes: 1 }], aliases: [fs8] } + - { id: 58, symbol: F25_D, name: f25_d, encoding: 25, dwarf_register: 57, units: [{ unit: U_F25, lanes: 1 }], aliases: [fs9] } + - { id: 59, symbol: F26_D, name: f26_d, encoding: 26, dwarf_register: 58, units: [{ unit: U_F26, lanes: 1 }], aliases: [fs10] } + - { id: 60, symbol: F27_D, name: f27_d, encoding: 27, dwarf_register: 59, units: [{ unit: U_F27, lanes: 1 }], aliases: [fs11] } + - { id: 61, symbol: F28_D, name: f28_d, encoding: 28, dwarf_register: 60, units: [{ unit: U_F28, lanes: 1 }], aliases: [ft8] } + - { id: 62, symbol: F29_D, name: f29_d, encoding: 29, dwarf_register: 61, units: [{ unit: U_F29, lanes: 1 }], aliases: [ft9] } + - { id: 63, symbol: F30_D, name: f30_d, encoding: 30, dwarf_register: 62, units: [{ unit: U_F30, lanes: 1 }], aliases: [ft10] } + - { id: 64, symbol: F31_D, name: f31_d, encoding: 31, dwarf_register: 63, units: [{ unit: U_F31, lanes: 1 }], aliases: [ft11] } + - { id: 65, symbol: F0_F, name: f0_f, encoding: 0, dwarf_register: 32, units: [{ unit: U_F0, lanes: 1 }] } + - { id: 66, symbol: F1_F, name: f1_f, encoding: 1, dwarf_register: 33, units: [{ unit: U_F1, lanes: 1 }] } + - { id: 67, symbol: F2_F, name: f2_f, encoding: 2, dwarf_register: 34, units: [{ unit: U_F2, lanes: 1 }] } + - { id: 68, symbol: F3_F, name: f3_f, encoding: 3, dwarf_register: 35, units: [{ unit: U_F3, lanes: 1 }] } + - { id: 69, symbol: F4_F, name: f4_f, encoding: 4, dwarf_register: 36, units: [{ unit: U_F4, lanes: 1 }] } + - { id: 70, symbol: F5_F, name: f5_f, encoding: 5, dwarf_register: 37, units: [{ unit: U_F5, lanes: 1 }] } + - { id: 71, symbol: F6_F, name: f6_f, encoding: 6, dwarf_register: 38, units: [{ unit: U_F6, lanes: 1 }] } + - { id: 72, symbol: F7_F, name: f7_f, encoding: 7, dwarf_register: 39, units: [{ unit: U_F7, lanes: 1 }] } + - { id: 73, symbol: F8_F, name: f8_f, encoding: 8, dwarf_register: 40, units: [{ unit: U_F8, lanes: 1 }] } + - { id: 74, symbol: F9_F, name: f9_f, encoding: 9, dwarf_register: 41, units: [{ unit: U_F9, lanes: 1 }] } + - { id: 75, symbol: F10_F, name: f10_f, encoding: 10, dwarf_register: 42, units: [{ unit: U_F10, lanes: 1 }] } + - { id: 76, symbol: F11_F, name: f11_f, encoding: 11, dwarf_register: 43, units: [{ unit: U_F11, lanes: 1 }] } + - { id: 77, symbol: F12_F, name: f12_f, encoding: 12, dwarf_register: 44, units: [{ unit: U_F12, lanes: 1 }] } + - { id: 78, symbol: F13_F, name: f13_f, encoding: 13, dwarf_register: 45, units: [{ unit: U_F13, lanes: 1 }] } + - { id: 79, symbol: F14_F, name: f14_f, encoding: 14, dwarf_register: 46, units: [{ unit: U_F14, lanes: 1 }] } + - { id: 80, symbol: F15_F, name: f15_f, encoding: 15, dwarf_register: 47, units: [{ unit: U_F15, lanes: 1 }] } + - { id: 81, symbol: F16_F, name: f16_f, encoding: 16, dwarf_register: 48, units: [{ unit: U_F16, lanes: 1 }] } + - { id: 82, symbol: F17_F, name: f17_f, encoding: 17, dwarf_register: 49, units: [{ unit: U_F17, lanes: 1 }] } + - { id: 83, symbol: F18_F, name: f18_f, encoding: 18, dwarf_register: 50, units: [{ unit: U_F18, lanes: 1 }] } + - { id: 84, symbol: F19_F, name: f19_f, encoding: 19, dwarf_register: 51, units: [{ unit: U_F19, lanes: 1 }] } + - { id: 85, symbol: F20_F, name: f20_f, encoding: 20, dwarf_register: 52, units: [{ unit: U_F20, lanes: 1 }] } + - { id: 86, symbol: F21_F, name: f21_f, encoding: 21, dwarf_register: 53, units: [{ unit: U_F21, lanes: 1 }] } + - { id: 87, symbol: F22_F, name: f22_f, encoding: 22, dwarf_register: 54, units: [{ unit: U_F22, lanes: 1 }] } + - { id: 88, symbol: F23_F, name: f23_f, encoding: 23, dwarf_register: 55, units: [{ unit: U_F23, lanes: 1 }] } + - { id: 89, symbol: F24_F, name: f24_f, encoding: 24, dwarf_register: 56, units: [{ unit: U_F24, lanes: 1 }] } + - { id: 90, symbol: F25_F, name: f25_f, encoding: 25, dwarf_register: 57, units: [{ unit: U_F25, lanes: 1 }] } + - { id: 91, symbol: F26_F, name: f26_f, encoding: 26, dwarf_register: 58, units: [{ unit: U_F26, lanes: 1 }] } + - { id: 92, symbol: F27_F, name: f27_f, encoding: 27, dwarf_register: 59, units: [{ unit: U_F27, lanes: 1 }] } + - { id: 93, symbol: F28_F, name: f28_f, encoding: 28, dwarf_register: 60, units: [{ unit: U_F28, lanes: 1 }] } + - { id: 94, symbol: F29_F, name: f29_f, encoding: 29, dwarf_register: 61, units: [{ unit: U_F29, lanes: 1 }] } + - { id: 95, symbol: F30_F, name: f30_f, encoding: 30, dwarf_register: 62, units: [{ unit: U_F30, lanes: 1 }] } + - { id: 96, symbol: F31_F, name: f31_f, encoding: 31, dwarf_register: 63, units: [{ unit: U_F31, lanes: 1 }] } + - { id: 97, symbol: FFLAGS, name: fflags, encoding: 0, dwarf_register: 65, units: [{ unit: U_FFLAGS, lanes: 1 }], artificial: true, reserved: true } + - { id: 98, symbol: FRM, name: frm, encoding: 0, dwarf_register: 66, units: [{ unit: U_FRM, lanes: 1 }], artificial: true, reserved: true } + - { id: 99, symbol: V0, name: v0, encoding: 0, dwarf_register: 96, units: [{ unit: U_V0, lanes: 1 }] } + - { id: 100, symbol: V1, name: v1, encoding: 1, dwarf_register: 97, units: [{ unit: U_V1, lanes: 1 }] } + - { id: 101, symbol: V2, name: v2, encoding: 2, dwarf_register: 98, units: [{ unit: U_V2, lanes: 1 }] } + - { id: 102, symbol: V3, name: v3, encoding: 3, dwarf_register: 99, units: [{ unit: U_V3, lanes: 1 }] } + - { id: 103, symbol: V4, name: v4, encoding: 4, dwarf_register: 100, units: [{ unit: U_V4, lanes: 1 }] } + - { id: 104, symbol: V5, name: v5, encoding: 5, dwarf_register: 101, units: [{ unit: U_V5, lanes: 1 }] } + - { id: 105, symbol: V6, name: v6, encoding: 6, dwarf_register: 102, units: [{ unit: U_V6, lanes: 1 }] } + - { id: 106, symbol: V7, name: v7, encoding: 7, dwarf_register: 103, units: [{ unit: U_V7, lanes: 1 }] } + - { id: 107, symbol: V8, name: v8, encoding: 8, dwarf_register: 104, units: [{ unit: U_V8, lanes: 1 }] } + - { id: 108, symbol: V9, name: v9, encoding: 9, dwarf_register: 105, units: [{ unit: U_V9, lanes: 1 }] } + - { id: 109, symbol: V10, name: v10, encoding: 10, dwarf_register: 106, units: [{ unit: U_V10, lanes: 1 }] } + - { id: 110, symbol: V11, name: v11, encoding: 11, dwarf_register: 107, units: [{ unit: U_V11, lanes: 1 }] } + - { id: 111, symbol: V12, name: v12, encoding: 12, dwarf_register: 108, units: [{ unit: U_V12, lanes: 1 }] } + - { id: 112, symbol: V13, name: v13, encoding: 13, dwarf_register: 109, units: [{ unit: U_V13, lanes: 1 }] } + - { id: 113, symbol: V14, name: v14, encoding: 14, dwarf_register: 110, units: [{ unit: U_V14, lanes: 1 }] } + - { id: 114, symbol: V15, name: v15, encoding: 15, dwarf_register: 111, units: [{ unit: U_V15, lanes: 1 }] } + - { id: 115, symbol: V16, name: v16, encoding: 16, dwarf_register: 112, units: [{ unit: U_V16, lanes: 1 }] } + - { id: 116, symbol: V17, name: v17, encoding: 17, dwarf_register: 113, units: [{ unit: U_V17, lanes: 1 }] } + - { id: 117, symbol: V18, name: v18, encoding: 18, dwarf_register: 114, units: [{ unit: U_V18, lanes: 1 }] } + - { id: 118, symbol: V19, name: v19, encoding: 19, dwarf_register: 115, units: [{ unit: U_V19, lanes: 1 }] } + - { id: 119, symbol: V20, name: v20, encoding: 20, dwarf_register: 116, units: [{ unit: U_V20, lanes: 1 }] } + - { id: 120, symbol: V21, name: v21, encoding: 21, dwarf_register: 117, units: [{ unit: U_V21, lanes: 1 }] } + - { id: 121, symbol: V22, name: v22, encoding: 22, dwarf_register: 118, units: [{ unit: U_V22, lanes: 1 }] } + - { id: 122, symbol: V23, name: v23, encoding: 23, dwarf_register: 119, units: [{ unit: U_V23, lanes: 1 }] } + - { id: 123, symbol: V24, name: v24, encoding: 24, dwarf_register: 120, units: [{ unit: U_V24, lanes: 1 }] } + - { id: 124, symbol: V25, name: v25, encoding: 25, dwarf_register: 121, units: [{ unit: U_V25, lanes: 1 }] } + - { id: 125, symbol: V26, name: v26, encoding: 26, dwarf_register: 122, units: [{ unit: U_V26, lanes: 1 }] } + - { id: 126, symbol: V27, name: v27, encoding: 27, dwarf_register: 123, units: [{ unit: U_V27, lanes: 1 }] } + - { id: 127, symbol: V28, name: v28, encoding: 28, dwarf_register: 124, units: [{ unit: U_V28, lanes: 1 }] } + - { id: 128, symbol: V29, name: v29, encoding: 29, dwarf_register: 125, units: [{ unit: U_V29, lanes: 1 }] } + - { id: 129, symbol: V30, name: v30, encoding: 30, dwarf_register: 126, units: [{ unit: U_V30, lanes: 1 }] } + - { id: 130, symbol: V31, name: v31, encoding: 31, dwarf_register: 127, units: [{ unit: U_V31, lanes: 1 }] } + +register_banks: + - { id: 1, symbol: GPR, name: GPRB, maximum_size_bits: 64 } + - { id: 2, symbol: FPR, name: FPRB, maximum_size_bits: 64 } + - { id: 3, symbol: CSR, name: CSRB, maximum_size_bits: 32 } + - { id: 4, symbol: VR, name: VRB, maximum_size_bits: 512 } + +register_classes: + - + id: 1 + symbol: GPR + name: GPR + bank: GPR + size_bits: 64 + spill_size_bits: 64 + spill_alignment_bits: 64 + lanes: 1 + registers: [X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] + allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] + - + id: 2 + symbol: GPRC + name: GPRC + bank: GPR + size_bits: 64 + spill_size_bits: 64 + spill_alignment_bits: 64 + lanes: 1 + registers: [X8, X9, X10, X11, X12, X13, X14, X15] + allocation_order: [X10, X11, X12, X13, X14, X15, X8, X9] + - + id: 3 + symbol: FPR64 + name: FPR64 + bank: FPR + size_bits: 64 + spill_size_bits: 64 + spill_alignment_bits: 64 + lanes: 1 + registers: [F0_D, F1_D, F2_D, F3_D, F4_D, F5_D, F6_D, F7_D, F8_D, F9_D, F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D, F28_D, F29_D, F30_D, F31_D] + allocation_order: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D, F0_D, F1_D, F2_D, F3_D, F4_D, F5_D, F6_D, F7_D, F28_D, F29_D, F30_D, F31_D, F8_D, F9_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D] + - + id: 4 + symbol: FPR64C + name: FPR64C + bank: FPR + size_bits: 64 + spill_size_bits: 64 + spill_alignment_bits: 64 + lanes: 1 + registers: [F8_D, F9_D, F10_D, F11_D, F12_D, F13_D, F14_D, F15_D] + allocation_order: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F8_D, F9_D] + - + id: 5 + symbol: FPR32 + name: FPR32 + bank: FPR + size_bits: 32 + spill_size_bits: 32 + spill_alignment_bits: 32 + lanes: 1 + registers: [F0_F, F1_F, F2_F, F3_F, F4_F, F5_F, F6_F, F7_F, F8_F, F9_F, F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F16_F, F17_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F, F28_F, F29_F, F30_F, F31_F] + allocation_order: [F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F16_F, F17_F, F0_F, F1_F, F2_F, F3_F, F4_F, F5_F, F6_F, F7_F, F28_F, F29_F, F30_F, F31_F, F8_F, F9_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F] + - + id: 6 + symbol: FPR32C + name: FPR32C + bank: FPR + size_bits: 32 + spill_size_bits: 32 + spill_alignment_bits: 32 + lanes: 1 + registers: [F8_F, F9_F, F10_F, F11_F, F12_F, F13_F, F14_F, F15_F] + allocation_order: [F10_F, F11_F, F12_F, F13_F, F14_F, F15_F, F8_F, F9_F] + - + id: 7 + symbol: GPR_NX0 + name: GPR_NX0 + bank: GPR + size_bits: 64 + spill_size_bits: 64 + spill_alignment_bits: 64 + lanes: 1 + registers: [X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] + allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] + - + id: 8 + symbol: GPR_NX0_NX2 + name: GPR_NX0_NX2 + bank: GPR + size_bits: 64 + spill_size_bits: 64 + spill_alignment_bits: 64 + lanes: 1 + registers: [X1, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] + allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] + - + id: 9 + symbol: FFLAGS + name: FFLAGS + bank: CSR + size_bits: 32 + spill_size_bits: 32 + spill_alignment_bits: 32 + lanes: 1 + registers: [FFLAGS] + allocation_order: [] + allocatable: false + - + id: 10 + symbol: FRM + name: FRM + bank: CSR + size_bits: 32 + spill_size_bits: 32 + spill_alignment_bits: 32 + lanes: 1 + registers: [FRM] + allocation_order: [] + allocatable: false + - + id: 11 + symbol: VR + name: VR + bank: VR + size_bits: 64 + spill_size_bits: 64 + spill_alignment_bits: 64 + lanes: 1 + registers: [V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31] + allocation_order: [] + allocatable: false + +register_masks: + - + name: CSR_ILP32_LP64 + preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27] + - + name: CSR_ILP32D_LP64D + preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, F8_D, F9_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D, F8_F, F9_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F] + +mir_operand_flags: + direct_mask: 127 + direct: + - { name: riscv-call, value: 1 } + - { name: riscv-pcrel-hi, value: 2 } + - { name: riscv-pcrel-lo, value: 4 } + - { name: riscv-copy-f32, value: 8 } + - { name: riscv-copy-f64, value: 16 } + - { name: riscv-hi, value: 32 } + - { name: riscv-lo, value: 64 } + bitmask: [] diff --git a/backend/utils/TableGen/CMakeLists.txt b/backend/utils/TableGen/CMakeLists.txt index 45b4bff..60fc769 100644 --- a/backend/utils/TableGen/CMakeLists.txt +++ b/backend/utils/TableGen/CMakeLists.txt @@ -5,9 +5,11 @@ set( AsmWriterEmitter.cpp CallingConvEmitter.cpp CodeEmitterGen.cpp + GlobalISelEmitter.cpp Common/CodeGenInstruction.cpp Common/CodeGenRegisters.cpp Common/CodeGenSchedule.cpp + Common/CodeGenSelection.cpp Common/CodeGenTarget.cpp InstrInfoEmitter.cpp RegisterBankEmitter.cpp diff --git a/backend/utils/TableGen/Common/CodeGenSelection.cpp b/backend/utils/TableGen/Common/CodeGenSelection.cpp new file mode 100644 index 0000000..0216136 --- /dev/null +++ b/backend/utils/TableGen/Common/CodeGenSelection.cpp @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-3.0-or-later + +#include "CodeGenTarget.h" +#include "rcc/CodeGen/GenericOpcodes.h" +#include "rcc/CodeGen/LowLevelType.h" + +#include <algorithm> +#include <cstdint> +#include <optional> +#include <ranges> +#include <string_view> +#include <unordered_set> +#include <utility> + +namespace rcc::targetgen { +namespace { + +[[nodiscard]] std::optional<std::uint32_t> genericOpcodeValue(std::string_view Symbol) { +#define RCC_CORE_OPCODE(Name) \ + if (Symbol == #Name) \ + return static_cast<std::uint32_t>(GenericOpcode::Name); +#define RCC_GENERIC_OPCODE(Name) RCC_CORE_OPCODE(Name) +#include "rcc/CodeGen/GenericOpcode.def" +#undef RCC_GENERIC_OPCODE +#undef RCC_CORE_OPCODE + return std::nullopt; +} + +[[nodiscard]] const NormalizedInstruction * +findInstructionBySymbol(const NormalizedTargetModel &Model, std::string_view Symbol) { + const auto Position = + std::ranges::find(Model.Instructions, Symbol, &NormalizedInstruction::Symbol); + return Position == Model.Instructions.end() ? nullptr : &*Position; +} + +[[nodiscard]] std::optional<std::uint32_t> resolveOpcode(const NormalizedTargetModel &Model, + std::string_view Symbol) { + if (const NormalizedInstruction *Instruction = findInstructionBySymbol(Model, Symbol)) + return Instruction->ID; + return genericOpcodeValue(Symbol); +} + +[[nodiscard]] bool isRegisterOperand(const NormalizedInstruction &Instruction, + std::uint32_t Index) { + return Index < Instruction.Operands.size() && + std::ranges::contains(Instruction.Operands[Index].Kinds, "Register"); +} + +} // namespace + +bool CodeGenTarget::normalizeSelectionRules(NormalizedTargetModel &Result) { + std::unordered_set<std::string> Symbols; + for (const SourceSelectionRule &Rule : Input.SelectionRules) { + const auto MatchOpcode = resolveOpcode(Result, Rule.MatchOpcodeSymbol); + const auto ResultOpcode = resolveOpcode(Result, Rule.ResultOpcodeSymbol); + const NormalizedInstruction *MatchInstruction = + findInstructionBySymbol(Result, Rule.MatchOpcodeSymbol); + const NormalizedInstruction *ResultInstruction = + findInstructionBySymbol(Result, Rule.ResultOpcodeSymbol); + if (!isIdentifier(Rule.Symbol) || !Symbols.insert(Rule.Symbol).second || !MatchOpcode || + !ResultOpcode) { + fail(Rule.Range, + "selection rules require a unique identifier and declared match/result opcodes"); + return false; + } + if (MatchInstruction != nullptr && !std::ranges::contains(MatchInstruction->Flags, "Generic")) { + fail(Rule.Range, "selection rule match opcode must be generic"); + return false; + } + if (isGenericOpcode(Opcode::fromValue(*ResultOpcode)) || + (ResultInstruction != nullptr && + std::ranges::contains(ResultInstruction->Flags, "Generic"))) { + fail(Rule.Range, "selection rule result opcode must not be generic"); + return false; + } + if (MatchInstruction != nullptr && ResultInstruction != nullptr && + ResultInstruction->Operands.size() != + MatchInstruction->Operands.size() + Rule.AppendedImmediates.size()) { + fail(Rule.Range, "selection rule result opcode has an incompatible operand count"); + return false; + } + + const auto NormalizeType = [this](const SourceSelectionTypePredicate &Source) + -> std::optional<NormalizedSelectionTypePredicate> { + NormalizedSelectionTypeKind Kind = NormalizedSelectionTypeKind::Any; + if (Source.Kind == "scalar") + Kind = NormalizedSelectionTypeKind::Scalar; + else if (Source.Kind == "pointer") + Kind = NormalizedSelectionTypeKind::Pointer; + else if (Source.Kind != "any") { + fail(Source.Range, "selection type kind must be 'any', 'scalar', or 'pointer'"); + return std::nullopt; + } + if (Source.Bits > LowLevelType::MaxBitWidth || + (Kind != NormalizedSelectionTypeKind::Any && Source.Bits == 0)) { + fail(Source.Range, "selection type bit width is invalid for its kind"); + return std::nullopt; + } + return NormalizedSelectionTypePredicate{.Kind = Kind, .Bits = Source.Bits}; + }; + + NormalizedSelectionRule Normalized; + Normalized.Symbol = Rule.Symbol; + Normalized.Priority = Rule.Priority; + Normalized.Specificity = 1; + Normalized.MatchOpcode = *MatchOpcode; + Normalized.ResultOpcode = *ResultOpcode; + Normalized.AppendedImmediates = Rule.AppendedImmediates; + if (Rule.ResultType) { + auto Type = NormalizeType(*Rule.ResultType); + if (!Type) + return false; + if (MatchInstruction != nullptr && !isRegisterOperand(*MatchInstruction, 0)) { + fail(Rule.ResultType->Range, + "selection result type predicate requires register operand zero"); + return false; + } + Normalized.ResultType = *Type; + ++Normalized.Specificity; + } + + std::unordered_set<std::uint32_t> TypeOperands; + for (const SourceSelectionOperandTypePredicate &Predicate : Rule.OperandTypes) { + auto Type = NormalizeType(Predicate.Type); + if (!Type) + return false; + if (!TypeOperands.insert(Predicate.OperandIndex).second || + (MatchInstruction != nullptr && + !isRegisterOperand(*MatchInstruction, Predicate.OperandIndex))) { + fail(Predicate.Range, + "selection operand type predicates require distinct register operands"); + return false; + } + Normalized.OperandTypes.push_back({.OperandIndex = Predicate.OperandIndex, .Type = *Type}); + ++Normalized.Specificity; + } + + std::unordered_set<std::uint32_t> BankOperands; + for (const SourceSelectionOperandBankPredicate &Predicate : Rule.OperandBanks) { + const auto Bank = BankBySymbol.find(Predicate.BankSymbol); + if (!BankOperands.insert(Predicate.OperandIndex).second || Bank == BankBySymbol.end() || + (MatchInstruction != nullptr && + !isRegisterOperand(*MatchInstruction, Predicate.OperandIndex))) { + fail(Predicate.Range, + "selection operand bank predicates require distinct register operands and declared " + "banks"); + return false; + } + Normalized.OperandBanks.push_back( + {.OperandIndex = Predicate.OperandIndex, .Bank = Bank->second}); + ++Normalized.Specificity; + } + + std::unordered_set<std::uint32_t> ClassOperands; + for (const SourceSelectionOperandClassPredicate &Predicate : Rule.OperandClasses) { + const auto RegClass = ClassBySymbol.find(Predicate.ClassSymbol); + if (!ClassOperands.insert(Predicate.OperandIndex).second || RegClass == ClassBySymbol.end() || + (MatchInstruction != nullptr && + !isRegisterOperand(*MatchInstruction, Predicate.OperandIndex))) { + fail(Predicate.Range, + "selection operand class predicates require distinct register operands and declared " + "classes"); + return false; + } + Normalized.OperandClasses.push_back( + {.OperandIndex = Predicate.OperandIndex, .RegClass = RegClass->second}); + ++Normalized.Specificity; + } + Result.SelectionRules.push_back(std::move(Normalized)); + } + + std::ranges::sort(Result.SelectionRules, + [](const NormalizedSelectionRule &Left, const NormalizedSelectionRule &Right) { + if (Left.Priority != Right.Priority) + return Left.Priority > Right.Priority; + if (Left.Specificity != Right.Specificity) + return Left.Specificity > Right.Specificity; + return Left.Symbol < Right.Symbol; + }); + return true; +} + +} // namespace rcc::targetgen diff --git a/backend/utils/TableGen/Common/CodeGenTarget.cpp b/backend/utils/TableGen/Common/CodeGenTarget.cpp index 89fea08..6d2e47e 100644 --- a/backend/utils/TableGen/Common/CodeGenTarget.cpp +++ b/backend/utils/TableGen/Common/CodeGenTarget.cpp @@ -35,7 +35,8 @@ CodeGenTarget::CodeGenTarget(const DescriptionAST &Input, std::string SourceName !normalizeMIROperandFlags(Result) || !normalizeCallingConventions(Result) || !normalizeNamedOperands(Result) || !normalizeImmediatePredicates(Result) || !normalizeSchedulingClasses(Result) || !normalizeEncodingCategories(Result) || - !normalizeAssemblyFormats(Result) || !normalizeInstructions(Result)) { + !normalizeAssemblyFormats(Result) || !normalizeInstructions(Result) || + !normalizeSelectionRules(Result)) { return std::nullopt; } std::ranges::sort(Result.RegisterUnits, {}, &SourceRegisterUnit::ID); @@ -214,6 +215,7 @@ DescriptionGenerationResult generateDescription(const std::string &SourceName, emitSubtarget(*Model) + emitCodeEmitter(*Model) + emitAssemblyWriter(*Model) + emitSearchableTables(*Model) + emitCallingConventions(*Model), + .GlobalISel = emitGlobalISel(*Model, DisplayName), }, .Diagnostics = {}, }; diff --git a/backend/utils/TableGen/Common/CodeGenTarget.h b/backend/utils/TableGen/Common/CodeGenTarget.h index cbddd4a..929d3e7 100644 --- a/backend/utils/TableGen/Common/CodeGenTarget.h +++ b/backend/utils/TableGen/Common/CodeGenTarget.h @@ -163,6 +163,45 @@ struct NormalizedInstruction final { std::string Deadline; }; +enum class NormalizedSelectionTypeKind : std::uint8_t { + Any, + Scalar, + Pointer, +}; + +struct NormalizedSelectionTypePredicate final { + NormalizedSelectionTypeKind Kind = NormalizedSelectionTypeKind::Any; + std::uint32_t Bits = 0; +}; + +struct NormalizedSelectionOperandTypePredicate final { + std::uint32_t OperandIndex = 0; + NormalizedSelectionTypePredicate Type; +}; + +struct NormalizedSelectionOperandBankPredicate final { + std::uint32_t OperandIndex = 0; + std::uint32_t Bank = 0; +}; + +struct NormalizedSelectionOperandClassPredicate final { + std::uint32_t OperandIndex = 0; + std::uint32_t RegClass = 0; +}; + +struct NormalizedSelectionRule final { + std::string Symbol; + std::uint32_t Priority = 0; + std::uint32_t Specificity = 0; + std::uint32_t MatchOpcode = 0; + std::optional<NormalizedSelectionTypePredicate> ResultType; + std::vector<NormalizedSelectionOperandTypePredicate> OperandTypes; + std::vector<NormalizedSelectionOperandBankPredicate> OperandBanks; + std::vector<NormalizedSelectionOperandClassPredicate> OperandClasses; + std::uint32_t ResultOpcode = 0; + std::vector<std::int64_t> AppendedImmediates; +}; + struct NormalizedTargetModel final { SourceTarget Target; std::vector<SourceRegisterUnit> RegisterUnits; @@ -178,6 +217,7 @@ struct NormalizedTargetModel final { std::vector<NormalizedEncodingCategory> EncodingCategories; std::vector<NormalizedAssemblyFormat> AssemblyFormats; std::vector<NormalizedInstruction> Instructions; + std::vector<NormalizedSelectionRule> SelectionRules; }; [[nodiscard]] std::optional<std::string_view> @@ -219,6 +259,7 @@ private: normalizeImplicitRegisters(const std::vector<SourceImplicitRegister> &InputRegisters, bool IsDef, std::vector<NormalizedImplicitRegister> &Result); [[nodiscard]] bool normalizeInstructions(NormalizedTargetModel &Result); + [[nodiscard]] bool normalizeSelectionRules(NormalizedTargetModel &Result); const DescriptionAST &Input; std::string SourceName; diff --git a/backend/utils/TableGen/GlobalISelEmitter.cpp b/backend/utils/TableGen/GlobalISelEmitter.cpp new file mode 100644 index 0000000..1634eb3 --- /dev/null +++ b/backend/utils/TableGen/GlobalISelEmitter.cpp @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-3.0-or-later + +#include "TableGenBackends.h" + +#include <cstddef> +#include <cstdint> +#include <ostream> +#include <sstream> +#include <string> +#include <string_view> + +namespace rcc::targetgen { +namespace { + +[[nodiscard]] std::string_view typeKindName(NormalizedSelectionTypeKind Kind) noexcept { + switch (Kind) { + case NormalizedSelectionTypeKind::Any: + return "Any"; + case NormalizedSelectionTypeKind::Scalar: + return "Scalar"; + case NormalizedSelectionTypeKind::Pointer: + return "Pointer"; + } + return "Any"; +} + +void emitInstruction(std::ostream &Output, std::string_view Opcode, std::uint32_t OperandIndex, + std::uint32_t Value = 0, std::string_view Auxiliary = "0", + std::int64_t Immediate = 0) { + Output << " {GIMatchTableOpcode::" << Opcode << ", " << OperandIndex << ", " << Value << ", " + << Auxiliary << ", " << Immediate << "},\n"; +} + +void emitTypePredicate(std::ostream &Output, std::uint32_t OperandIndex, + const NormalizedSelectionTypePredicate &Predicate) { + emitInstruction(Output, "CheckOperandType", OperandIndex, Predicate.Bits, + "static_cast<std::uint32_t>(GIMatchTypeKind::" + + std::string(typeKindName(Predicate.Kind)) + ")"); +} + +[[nodiscard]] std::size_t instructionCount(const NormalizedSelectionRule &Rule) noexcept { + return 3U + (Rule.ResultType ? 1U : 0U) + Rule.OperandTypes.size() + Rule.OperandBanks.size() + + Rule.OperandClasses.size() + Rule.AppendedImmediates.size(); +} + +} // namespace + +std::string emitGlobalISel(const NormalizedTargetModel &Model, std::string_view SourceName) { + std::size_t InstructionCount = 0; + for (const NormalizedSelectionRule &Rule : Model.SelectionRules) + InstructionCount += instructionCount(Rule); + + std::ostringstream Output; + Output << "// SPDX-License-Identifier: GPL-3.0-or-later\n\n"; + Output << "// This file is generated by rcc-tblgen from "; + appendQuoted(Output, SourceName); + Output << ". Do not edit it manually.\n\n"; + Output << "#ifdef GET_GLOBALISEL_MATCH_TABLE\n\n"; + Output << "constexpr std::array<GIMatchTableInstruction, " << InstructionCount + << "> GeneratedGlobalISelInstructions = {{\n"; + for (const NormalizedSelectionRule &Rule : Model.SelectionRules) { + emitInstruction(Output, "CheckOpcode", 0, Rule.MatchOpcode); + if (Rule.ResultType) + emitTypePredicate(Output, 0, *Rule.ResultType); + for (const NormalizedSelectionOperandTypePredicate &Predicate : Rule.OperandTypes) + emitTypePredicate(Output, Predicate.OperandIndex, Predicate.Type); + for (const NormalizedSelectionOperandBankPredicate &Predicate : Rule.OperandBanks) + emitInstruction(Output, "CheckOperandBank", Predicate.OperandIndex, Predicate.Bank); + for (const NormalizedSelectionOperandClassPredicate &Predicate : Rule.OperandClasses) + emitInstruction(Output, "CheckOperandClass", Predicate.OperandIndex, Predicate.RegClass); + emitInstruction(Output, "MutateOpcode", 0, Rule.ResultOpcode); + for (const std::int64_t Immediate : Rule.AppendedImmediates) + emitInstruction(Output, "AppendImmediate", 0, 0, "0", Immediate); + emitInstruction(Output, "Complete", 0); + } + Output << "}};\n\n"; + + Output << "constexpr std::array<GIMatchTableRule, " << Model.SelectionRules.size() + << "> GeneratedGlobalISelRules = {{\n"; + std::size_t FirstInstruction = 0; + for (const NormalizedSelectionRule &Rule : Model.SelectionRules) { + const std::size_t Count = instructionCount(Rule); + Output << " {"; + appendQuoted(Output, Rule.Symbol); + Output << ", " << Rule.Priority << ", " << FirstInstruction << ", " << Count << "},\n"; + FirstInstruction += Count; + } + Output << "}};\n\n"; + Output << "[[nodiscard]] constexpr GIMatchTable generatedGlobalISelMatchTable() noexcept {\n" + " return {GeneratedGlobalISelInstructions, GeneratedGlobalISelRules};\n" + "}\n\n"; + Output << "#endif // GET_GLOBALISEL_MATCH_TABLE\n"; + return Output.str(); +} + +} // namespace rcc::targetgen diff --git a/backend/utils/TableGen/TableGenBackends.h b/backend/utils/TableGen/TableGenBackends.h index 7835efb..a5f283e 100644 --- a/backend/utils/TableGen/TableGenBackends.h +++ b/backend/utils/TableGen/TableGenBackends.h @@ -17,6 +17,7 @@ struct GeneratedDescription final { std::string RegisterHeader; std::string InstructionHeader; std::string TargetTables; + std::string GlobalISel; }; struct DescriptionGenerationResult final { @@ -41,6 +42,8 @@ struct DescriptionGenerationResult final { [[nodiscard]] std::string emitAssemblyWriter(const NormalizedTargetModel &Model); [[nodiscard]] std::string emitSubtarget(const NormalizedTargetModel &Model); [[nodiscard]] std::string emitSearchableTables(const NormalizedTargetModel &Model); +[[nodiscard]] std::string emitGlobalISel(const NormalizedTargetModel &Model, + std::string_view SourceName); [[nodiscard]] DescriptionGenerationResult generateDescription(const std::string &SourceName, std::string SourceText); diff --git a/backend/utils/TableGen/rcc-tblgen.cpp b/backend/utils/TableGen/rcc-tblgen.cpp index 3e4e093..45690ee 100644 --- a/backend/utils/TableGen/rcc-tblgen.cpp +++ b/backend/utils/TableGen/rcc-tblgen.cpp @@ -3,38 +3,51 @@ #include "TableGenBackends.h" #include "rcc/Support/TextDiagnostic.h" +#include <cctype> #include <filesystem> #include <fstream> #include <iostream> #include <iterator> +#include <optional> #include <string> #include <string_view> +#include <unordered_map> +#include <vector> namespace { struct CommandLine final { - std::string InputPath; + std::vector<std::string> InputPaths; std::string RegisterHeaderPath; std::string InstructionHeaderPath; std::string TablesPath; + std::string GlobalISelPath; }; [[nodiscard]] bool parseCommandLine(int ArgumentCount, char *Arguments[], CommandLine &Result) { for (int Index = 1; Index < ArgumentCount; ++Index) { const std::string_view Argument(Arguments[Index]); - if (Argument == "--input" || Argument == "--register-header" || - Argument == "--instruction-header" || Argument == "--tables") { + if (Argument == "--input") { + if (Index + 1 >= ArgumentCount) { + std::cerr << "rcc-tblgen: missing value for " << Argument << '\n'; + return false; + } + Result.InputPaths.emplace_back(Arguments[++Index]); + continue; + } + if (Argument == "--register-header" || Argument == "--instruction-header" || + Argument == "--tables" || Argument == "--global-isel") { if (Index + 1 >= ArgumentCount) { std::cerr << "rcc-tblgen: missing value for " << Argument << '\n'; return false; } std::string *Destination = nullptr; - if (Argument == "--input") - Destination = &Result.InputPath; - else if (Argument == "--register-header") + if (Argument == "--register-header") Destination = &Result.RegisterHeaderPath; else if (Argument == "--instruction-header") Destination = &Result.InstructionHeaderPath; + else if (Argument == "--global-isel") + Destination = &Result.GlobalISelPath; else Destination = &Result.TablesPath; *Destination = Arguments[++Index]; @@ -43,12 +56,13 @@ struct CommandLine final { std::cerr << "rcc-tblgen: unknown argument '" << Argument << "'\n"; return false; } - if (!Result.InputPath.empty() && !Result.RegisterHeaderPath.empty() && - !Result.InstructionHeaderPath.empty() && !Result.TablesPath.empty()) { + if (!Result.InputPaths.empty() && !Result.RegisterHeaderPath.empty() && + !Result.InstructionHeaderPath.empty() && !Result.TablesPath.empty() && + !Result.GlobalISelPath.empty()) { return true; } - std::cerr << "usage: rcc-tblgen --input <file> --register-header <file> " - "--instruction-header <file> --tables <file>\n"; + std::cerr << "usage: rcc-tblgen --input <file> [--input <fragment>]... --register-header <file> " + "--instruction-header <file> --tables <file> --global-isel <file>\n"; return false; } @@ -74,6 +88,107 @@ struct CommandLine final { return false; } +struct SourceSection final { + std::string Name; + std::string Contents; + std::size_t HeaderSize = 0; +}; + +[[nodiscard]] bool isIdentifierCharacter(char Character) noexcept { + return std::isalnum(static_cast<unsigned char>(Character)) != 0 || Character == '_'; +} + +[[nodiscard]] std::optional<std::string_view> topLevelKey(std::string_view Line) noexcept { + if (Line.empty() || Line.front() == '#' || + (!std::isalpha(static_cast<unsigned char>(Line.front())) && Line.front() != '_')) { + return std::nullopt; + } + std::size_t End = 1; + while (End < Line.size() && isIdentifierCharacter(Line[End])) + ++End; + if (End == Line.size() || Line[End] != ':') + return std::nullopt; + return Line.substr(0, End); +} + +[[nodiscard]] std::vector<SourceSection> splitSections(std::string_view SourceText) { + std::vector<SourceSection> Result; + std::size_t SectionStart = 0; + std::size_t HeaderEnd = 0; + std::optional<std::string> SectionName; + std::size_t LineStart = 0; + while (LineStart < SourceText.size()) { + const std::size_t LineEnd = SourceText.find('\n', LineStart); + const std::size_t ContentEnd = LineEnd == std::string_view::npos ? SourceText.size() : LineEnd; + const std::string_view Line = SourceText.substr(LineStart, ContentEnd - LineStart); + if (const auto Key = topLevelKey(Line)) { + if (SectionName) { + Result.push_back({ + .Name = std::move(*SectionName), + .Contents = std::string(SourceText.substr(SectionStart, LineStart - SectionStart)), + .HeaderSize = HeaderEnd - SectionStart, + }); + } + SectionStart = LineStart; + HeaderEnd = LineEnd == std::string_view::npos ? SourceText.size() : LineEnd + 1U; + SectionName = std::string(*Key); + } + if (LineEnd == std::string_view::npos) + break; + LineStart = LineEnd + 1U; + } + if (SectionName) { + Result.push_back({ + .Name = std::move(*SectionName), + .Contents = std::string(SourceText.substr(SectionStart)), + .HeaderSize = HeaderEnd - SectionStart, + }); + } + return Result; +} + +[[nodiscard]] std::optional<std::string> +combineDescriptionSources(const std::vector<std::string> &Paths, + const std::vector<std::string> &Sources) { + std::vector<SourceSection> Result; + std::unordered_map<std::string, std::size_t> SectionIndex; + for (std::size_t Index = 0; Index < Sources.size(); ++Index) { + const std::vector<SourceSection> Sections = splitSections(Sources[Index]); + if (Sections.empty()) { + std::cerr << "rcc-tblgen: input '" << Paths[Index] + << "' does not contain a top-level description section\n"; + return std::nullopt; + } + for (const SourceSection &Section : Sections) { + const auto Position = SectionIndex.find(Section.Name); + if (Position == SectionIndex.end()) { + SectionIndex.emplace(Section.Name, Result.size()); + Result.push_back(Section); + continue; + } + if (Section.Name != "instructions" && Section.Name != "selection_rules") { + std::cerr << "rcc-tblgen: duplicate description section '" << Section.Name << "' in '" + << Paths[Index] << "'\n"; + return std::nullopt; + } + SourceSection &Existing = Result[Position->second]; + const std::string_view Body(Section.Contents.data() + Section.HeaderSize, + Section.Contents.size() - Section.HeaderSize); + if (!Existing.Contents.empty() && Existing.Contents.back() != '\n') + Existing.Contents.push_back('\n'); + Existing.Contents.append(Body); + } + } + + std::string Combined; + for (const SourceSection &Section : Result) { + if (!Combined.empty() && Combined.back() != '\n') + Combined.push_back('\n'); + Combined.append(Section.Contents); + } + return Combined; +} + } // namespace int main(int ArgumentCount, char *Arguments[]) { @@ -81,17 +196,23 @@ int main(int ArgumentCount, char *Arguments[]) { if (!parseCommandLine(ArgumentCount, Arguments, Command)) return 1; - std::ifstream Input(Command.InputPath, std::ios::binary); - if (!Input) { - std::cerr << "rcc-tblgen: cannot open input '" << Command.InputPath << "'\n"; - return 1; + std::vector<std::string> Sources; + Sources.reserve(Command.InputPaths.size()); + for (const std::string &InputPath : Command.InputPaths) { + std::ifstream Input(InputPath, std::ios::binary); + if (!Input) { + std::cerr << "rcc-tblgen: cannot open input '" << InputPath << "'\n"; + return 1; + } + Sources.emplace_back(std::istreambuf_iterator<char>(Input), std::istreambuf_iterator<char>()); } - const std::string SourceText{std::istreambuf_iterator<char>(Input), - std::istreambuf_iterator<char>()}; + const auto SourceText = combineDescriptionSources(Command.InputPaths, Sources); + if (!SourceText) + return 1; const rcc::targetgen::DescriptionGenerationResult Result = - rcc::targetgen::generateDescription(Command.InputPath, SourceText); + rcc::targetgen::generateDescription(Command.InputPaths.front(), *SourceText); if (!Result.succeeded()) { - const rcc::TextSource Source(Command.InputPath, SourceText); + const rcc::TextSource Source(Command.InputPaths.front(), *SourceText); for (const rcc::TextDiagnostic &Diagnostic : Result.Diagnostics) std::cerr << rcc::formatTextDiagnostic(Diagnostic, Source) << '\n'; return 1; @@ -104,7 +225,8 @@ int main(int ArgumentCount, char *Arguments[]) { const rcc::targetgen::GeneratedDescription &Output = Result.Output.value(); return writeFile(Command.RegisterHeaderPath, Output.RegisterHeader) && writeFile(Command.InstructionHeaderPath, Output.InstructionHeader) && - writeFile(Command.TablesPath, Output.TargetTables) + writeFile(Command.TablesPath, Output.TargetTables) && + writeFile(Command.GlobalISelPath, Output.GlobalISel) ? 0 : 1; } |