diff options
Diffstat (limited to 'rv64cpu/rtl/core')
| -rw-r--r-- | rv64cpu/rtl/core/decoder.sv | 2 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/ex_mem_reg.sv | 24 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/ex_stage.sv | 28 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/id_ex_reg.sv | 27 |
4 files changed, 64 insertions, 17 deletions
diff --git a/rv64cpu/rtl/core/decoder.sv b/rv64cpu/rtl/core/decoder.sv index 585a018..c948646 100644 --- a/rv64cpu/rtl/core/decoder.sv +++ b/rv64cpu/rtl/core/decoder.sv @@ -80,7 +80,7 @@ module decoder assign opcode = instr[6:0]; assign rd_addr = instr[11:7]; assign funct3 = instr[14:12]; - assign rs1_addr = instr[19:15]; + assign rs1_addr = (opcode == OPCODE_LUI) ? 5'b00000 : instr[19:15]; assign rs2_addr = instr[24:20]; assign funct7 = instr[31:25]; diff --git a/rv64cpu/rtl/core/ex_mem_reg.sv b/rv64cpu/rtl/core/ex_mem_reg.sv index 4fcf140..a8182aa 100644 --- a/rv64cpu/rtl/core/ex_mem_reg.sv +++ b/rv64cpu/rtl/core/ex_mem_reg.sv @@ -107,7 +107,7 @@ module ex_mem_reg ); always_ff @(posedge clk) begin - if (rst || flush_en) begin + if (rst) begin mem_alu_result <= '0; mem_branch_taken <= '0; mem_branch_target <= '0; @@ -138,6 +138,28 @@ module ex_mem_reg mem_is_fence <= '0; mem_is_fence_i <= '0; + end else if (flush_en) begin + // Critical control signals must be zeroed out + mem_branch_taken <= '0; + mem_is_load <= '0; + mem_is_store <= '0; + mem_mem_size <= '0; + mem_reg_write_en <= '0; + mem_rd_addr <= '0; + mem_wb_sel <= '0; + + // Exceptions and system control + mem_is_csr <= '0; + mem_csr_op <= '0; + mem_illegal_instr <= '0; + mem_is_ecall <= '0; + mem_is_ebreak <= '0; + mem_is_mret <= '0; + mem_is_sret <= '0; + mem_is_wfi <= '0; + mem_is_sfence_vma <= '0; + mem_is_fence <= '0; + mem_is_fence_i <= '0; end else if (~stall_en) begin mem_alu_result <= ex_alu_result; mem_branch_taken <= ex_branch_taken; diff --git a/rv64cpu/rtl/core/ex_stage.sv b/rv64cpu/rtl/core/ex_stage.sv index 0991b50..48d4833 100644 --- a/rv64cpu/rtl/core/ex_stage.sv +++ b/rv64cpu/rtl/core/ex_stage.sv @@ -42,17 +42,17 @@ module ex_stage output logic [XLEN-1:0] ex_branch_target ); - logic [XLEN-1:0] alumux_a; - logic [XLEN-1:0] alumux_b; + logic [XLEN-1:0] alu_mux_a; + logic [XLEN-1:0] alu_mux_b; logic [XLEN-1:0] alu_operand_a; logic [XLEN-1:0] alu_operand_b; logic [XLEN-1:0] alu_raw_result; - logic bu_branch_taken; + logic branch_unit_taken; // ------------- // ALU Input Multiplexers (MUX) - assign alumux_a = (ex_alu_src1_sel == 1'b1) ? ex_pc : ex_rs1_rdata; - assign alumux_b = (ex_alu_src2_sel == 1'b1) ? ex_imm : ex_rs2_rdata; + assign alu_mux_a = (ex_alu_src1_sel == 1'b1) ? ex_pc : ex_rs1_rdata; + assign alu_mux_b = (ex_alu_src2_sel == 1'b1) ? ex_imm : ex_rs2_rdata; // ------------- // RV64 Word Operation (32-bit) Pre-conditioning @@ -62,21 +62,21 @@ module ex_stage if (ex_is_word_op) begin // Shift operations require specific 32-bit extension forms if (ex_alu_op == ALU_SRA) - alu_operand_a = { {32{alumux_a[31]}}, alumux_a[31:0] }; // Sign extend for arithmetic shift + alu_operand_a = { {32{alu_mux_a[31]}}, alu_mux_a[31:0] }; // Sign extend for arithmetic shift else if (ex_alu_op == ALU_SRL) - alu_operand_a = { 32'b0, alumux_a[31:0] }; // Zero extend for logical shift + alu_operand_a = { 32'b0, alu_mux_a[31:0] }; // Zero extend for logical shift else - alu_operand_a = alumux_a; // ADDW/SUBW/SLLW don't care about upper bits + alu_operand_a = alu_mux_a; // ADDW/SUBW/SLLW don't care about upper bits // RV32 shift amount is strictly 5 bits (0-31), ignoring bit 5 which might be set in 64-bit registers if (ex_alu_op == ALU_SLL || ex_alu_op == ALU_SRL || ex_alu_op == ALU_SRA) - alu_operand_b = { 59'b0, alumux_b[4:0] }; + alu_operand_b = { 59'b0, alu_mux_b[4:0] }; else - alu_operand_b = alumux_b; + alu_operand_b = alu_mux_b; end else begin // 64-bit operations pass through unchanged - alu_operand_a = alumux_a; - alu_operand_b = alumux_b; + alu_operand_a = alu_mux_a; + alu_operand_b = alu_mux_b; end end @@ -96,7 +96,7 @@ module ex_stage .branch_op (ex_branch_op), .operand_a (ex_rs1_rdata), .operand_b (ex_rs2_rdata), - .branch_taken (bu_branch_taken) + .branch_taken (branch_unit_taken) ); // ------------- @@ -109,6 +109,6 @@ module ex_stage // Branch Target Calculation assign ex_branch_target = alu_raw_result & ~64'b1; - assign ex_branch_taken = ex_is_jump | (ex_is_branch & bu_branch_taken); + assign ex_branch_taken = ex_is_jump | (ex_is_branch & branch_unit_taken); endmodule diff --git a/rv64cpu/rtl/core/id_ex_reg.sv b/rv64cpu/rtl/core/id_ex_reg.sv index 7c780ee..e88ce17 100644 --- a/rv64cpu/rtl/core/id_ex_reg.sv +++ b/rv64cpu/rtl/core/id_ex_reg.sv @@ -113,7 +113,7 @@ module id_ex_reg ); always_ff @(posedge clk) begin - if (rst || flush_en) begin + if (rst) begin ex_pc <= '0; ex_rs1_rdata <= '0; ex_rs2_rdata <= '0; @@ -144,6 +144,31 @@ module id_ex_reg ex_is_sfence_vma <= '0; ex_is_fence <= '0; ex_is_fence_i <= '0; + end else if (flush_en) begin + ex_alu_op <= ALU_ADD; // NOP is effectively ADD x0, x0, 0 + ex_alu_src1_sel <= '0; + ex_alu_src2_sel <= '0; + ex_is_word_op <= '0; + ex_is_branch <= '0; + ex_branch_op <= BRANCH_EQ; + ex_is_jump <= '0; + ex_is_load <= '0; + ex_is_store <= '0; + ex_mem_size <= '0; + ex_reg_write_en <= '0; // VERY IMPORTANT: Do not write to regfile on NOP + ex_rd_addr <= '0; + ex_wb_sel <= '0; + ex_is_csr <= '0; + ex_csr_op <= '0; + ex_illegal_instr <= '0; + ex_is_ecall <= '0; + ex_is_ebreak <= '0; + ex_is_mret <= '0; + ex_is_sret <= '0; + ex_is_wfi <= '0; + ex_is_sfence_vma <= '0; + ex_is_fence <= '0; + ex_is_fence_i <= '0; end else if (~stall_en) begin ex_pc <= id_pc; ex_rs1_rdata <= id_rs1_rdata; |