diff options
Diffstat (limited to 'rv64cpu/rtl')
| -rw-r--r-- | rv64cpu/rtl/core/ex_mem_reg.sv | 8 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/mem_stage.sv | 18 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/mem_wb_reg.sv | 6 |
3 files changed, 16 insertions, 16 deletions
diff --git a/rv64cpu/rtl/core/ex_mem_reg.sv b/rv64cpu/rtl/core/ex_mem_reg.sv index a8182aa..2cc5e9e 100644 --- a/rv64cpu/rtl/core/ex_mem_reg.sv +++ b/rv64cpu/rtl/core/ex_mem_reg.sv @@ -37,7 +37,7 @@ module ex_mem_reg // ---------------------- // Bypassed Inputs from ID/EX Register - + // Data/Operands input logic [XLEN-1:0] ex_rs1_rdata, // Needed for CSRRW/RS/RC input logic [XLEN-1:0] ex_rs2_rdata, // Needed for store data @@ -116,7 +116,7 @@ module ex_mem_reg mem_rs1_addr <= '0; mem_pc <= '0; mem_imm <= '0; - + // Critical control signals must be zeroed out mem_is_load <= '0; mem_is_store <= '0; @@ -169,14 +169,14 @@ module ex_mem_reg mem_rs1_addr <= ex_rs1_addr; mem_pc <= ex_pc; mem_imm <= ex_imm; - + mem_is_load <= ex_is_load; mem_is_store <= ex_is_store; mem_mem_size <= ex_mem_size; mem_reg_write_en <= ex_reg_write_en; mem_rd_addr <= ex_rd_addr; mem_wb_sel <= ex_wb_sel; - + mem_is_csr <= ex_is_csr; mem_csr_op <= ex_csr_op; mem_illegal_instr <= ex_illegal_instr; diff --git a/rv64cpu/rtl/core/mem_stage.sv b/rv64cpu/rtl/core/mem_stage.sv index 467ba1b..a63a456 100644 --- a/rv64cpu/rtl/core/mem_stage.sv +++ b/rv64cpu/rtl/core/mem_stage.sv @@ -31,12 +31,12 @@ module mem_stage input logic [4:0] mem_rs1_addr, input logic [XLEN-1:0] mem_pc, input logic [XLEN-1:0] mem_imm, - + // Memory Control input logic mem_is_load, input logic mem_is_store, input logic [2:0] mem_mem_size, // LB/LH/LW/LD/LBU/LHU/LWU - + // Writeback Control input logic mem_reg_write_en, input logic [4:0] mem_rd_addr, @@ -69,7 +69,7 @@ module mem_stage output logic [XLEN-1:0] mem_wb_alu_result, output logic [XLEN-1:0] mem_wb_mem_rdata, output logic [XLEN-1:0] mem_wb_pc, - + output logic mem_wb_reg_write_en, output logic [4:0] mem_wb_rd_addr, output logic [1:0] mem_wb_wb_sel, @@ -79,7 +79,7 @@ module mem_stage output logic [XLEN-1:0] mem_wb_rs1_rdata, output logic [4:0] mem_wb_rs1_addr, output logic [XLEN-1:0] mem_wb_imm, - + output logic mem_wb_illegal_instr, output logic mem_wb_is_ecall, output logic mem_wb_is_ebreak, @@ -119,7 +119,7 @@ module mem_stage logic [2:0] align_offset; store_data_aligned = '0; write_strobe = 8'b0000_0000; - + // Mem address lower 3 bits determine the alignment within the 64-bit word align_offset = mem_alu_result[2:0]; @@ -152,7 +152,7 @@ module mem_stage endcase end end - + assign dmem_wdata = store_data_aligned; assign dmem_wstrb = write_strobe; @@ -163,9 +163,9 @@ module mem_stage logic [2:0] align_offset; logic [XLEN-1:0] shifted_rdata; load_data_aligned = '0; - + align_offset = mem_alu_result[2:0]; - + // Shift data down so the target bytes are at the bottom shifted_rdata = dmem_rdata >> (align_offset * 8); @@ -194,7 +194,7 @@ module mem_stage assign mem_wb_alu_result = mem_alu_result; assign mem_wb_mem_rdata = load_data_aligned; assign mem_wb_pc = mem_pc; - + assign mem_wb_reg_write_en = mem_reg_write_en; assign mem_wb_rd_addr = mem_rd_addr; assign mem_wb_wb_sel = mem_wb_sel; diff --git a/rv64cpu/rtl/core/mem_wb_reg.sv b/rv64cpu/rtl/core/mem_wb_reg.sv index eca60bc..a70057c 100644 --- a/rv64cpu/rtl/core/mem_wb_reg.sv +++ b/rv64cpu/rtl/core/mem_wb_reg.sv @@ -26,7 +26,7 @@ module mem_wb_reg // ----------------------- // Control Signals from Hazard Unit - input logic stall_en, + input logic stall_en, input logic flush_en, // ----------------------- @@ -53,7 +53,7 @@ module mem_wb_reg input logic mem_is_ebreak, input logic mem_is_mret, input logic mem_is_sret, - + // ----------------------- // Outputs to WB Stage // ----------------------- @@ -78,7 +78,7 @@ module mem_wb_reg output logic wb_is_ebreak, output logic wb_is_mret, output logic wb_is_sret - + ); // Sequential Logic: State Update always_ff @(posedge clk) begin |