diff options
Diffstat (limited to 'rv64cpu/tb/unit')
| -rw-r--r-- | rv64cpu/tb/unit/tb_ex_mem_reg.cc | 12 | ||||
| -rw-r--r-- | rv64cpu/tb/unit/tb_mem_stage.cc | 2 | ||||
| -rw-r--r-- | rv64cpu/tb/unit/tb_mem_wb_reg.cc | 12 |
3 files changed, 13 insertions, 13 deletions
diff --git a/rv64cpu/tb/unit/tb_ex_mem_reg.cc b/rv64cpu/tb/unit/tb_ex_mem_reg.cc index db1fe8b..75e5502 100644 --- a/rv64cpu/tb/unit/tb_ex_mem_reg.cc +++ b/rv64cpu/tb/unit/tb_ex_mem_reg.cc @@ -53,7 +53,7 @@ int main(int argc, char** argv) { // 1. Init / Reset dut->stall_en = 0; dut->flush_en = 0; - + // Set some random dangerous EX inputs dut->ex_pc = 0x80001000; dut->ex_rs1_rdata = 0x11111111; @@ -119,7 +119,7 @@ int main(int argc, char** argv) { dut->ex_rd_addr = 20; dut->ex_reg_write_en = 0; dut->ex_is_load = 0; - + tick(dut); check(dut->mem_pc == 0x80002000, "Stall_Maintains_PC"); @@ -147,19 +147,19 @@ int main(int argc, char** argv) { dut->ex_branch_taken = 1; dut->ex_reg_write_en = 1; dut->ex_is_store = 1; - + tick(dut); check(dut->mem_pc == 0x80003000, "Flush_Maintains_PC"); check(dut->mem_branch_taken == 0, "Flush_Clears_BranchTaken"); - check(dut->mem_reg_write_en == 0, "Flush_Clears_RegWrite"); - check(dut->mem_is_store == 0, "Flush_Clears_StoreEn"); + check(dut->mem_reg_write_en == 0, "Flush_Clears_RegWrite"); + check(dut->mem_is_store == 0, "Flush_Clears_StoreEn"); // 5. Flush Overrides Stall dut->flush_en = 0; dut->ex_pc = 0x80005000; dut->ex_reg_write_en = 1; - tick(dut); + tick(dut); check(dut->mem_pc == 0x80005000, "Pre_FlushStall_Setup"); dut->flush_en = 1; diff --git a/rv64cpu/tb/unit/tb_mem_stage.cc b/rv64cpu/tb/unit/tb_mem_stage.cc index 088ddbd..2747ca9 100644 --- a/rv64cpu/tb/unit/tb_mem_stage.cc +++ b/rv64cpu/tb/unit/tb_mem_stage.cc @@ -192,7 +192,7 @@ int main(int argc, char** argv) { tick(dut); check(dut->mem_stall_req == 1, "Stall_On_Req_NotReady"); - dut->dmem_req_ready = 1; + dut->dmem_req_ready = 1; dut->dmem_rsp_valid = 0; // Read request accepted, but data not valid yet tick(dut); check(dut->mem_stall_req == 1, "Stall_On_Rsp_NotValid"); diff --git a/rv64cpu/tb/unit/tb_mem_wb_reg.cc b/rv64cpu/tb/unit/tb_mem_wb_reg.cc index 0260c64..e91a354 100644 --- a/rv64cpu/tb/unit/tb_mem_wb_reg.cc +++ b/rv64cpu/tb/unit/tb_mem_wb_reg.cc @@ -53,7 +53,7 @@ int main(int argc, char** argv) { // 1. Init / Reset dut->stall_en = 0; dut->flush_en = 0; - + // Set some dangerous inputs dut->mem_pc = 0x80001000; dut->mem_alu_result = 0x11111111; @@ -113,7 +113,7 @@ int main(int argc, char** argv) { dut->mem_pc = 0x80003000; dut->mem_rd_addr = 20; dut->mem_reg_write_en = 0; - + tick(dut); check(dut->wb_pc == 0x80002000, "Stall_Maintains_PC"); @@ -133,19 +133,19 @@ int main(int argc, char** argv) { dut->mem_alu_result = 0xCCCCCCCC; dut->mem_reg_write_en = 1; dut->mem_is_csr = 1; - + tick(dut); check(dut->wb_pc == 0x80003000, "Flush_Maintains_PC"); check(dut->wb_alu_result == 0xAAAAAAAA, "Flush_Maintains_ALU"); - check(dut->wb_reg_write_en == 0, "Flush_Clears_RegWrite"); - check(dut->wb_is_csr == 0, "Flush_Clears_IsCSR"); + check(dut->wb_reg_write_en == 0, "Flush_Clears_RegWrite"); + check(dut->wb_is_csr == 0, "Flush_Clears_IsCSR"); // 5. Flush Overrides Stall dut->flush_en = 0; dut->mem_pc = 0x80005000; dut->mem_reg_write_en = 1; - tick(dut); + tick(dut); check(dut->wb_pc == 0x80005000, "Pre_FlushStall_Setup"); dut->flush_en = 1; |