diff options
Diffstat (limited to 'rv64cpu')
41 files changed, 2185 insertions, 0 deletions
diff --git a/rv64cpu/.github/workflows/ci.yml b/rv64cpu/.github/workflows/ci.yml new file mode 100644 index 0000000..03551fa --- /dev/null +++ b/rv64cpu/.github/workflows/ci.yml @@ -0,0 +1,64 @@ +name: CI + +on: + push: + branches: [ main, develop ] + pull_request: + branches: [ main ] + +jobs: + verilator-build: + name: Verilator Build & Test + runs-on: ubuntu-latest + + steps: + - name: Checkout + uses: actions/checkout@v4 + with: + submodules: recursive + + - name: Install dependencies + run: | + sudo apt-get update + sudo apt-get install -y \ + verilator \ + cmake \ + build-essential \ + git \ + autoconf \ + flex \ + bison \ + libfl-dev + + - name: Check Verilator version + run: verilator --version + + - name: Configure + run: cmake -B build -DENABLE_TRACE=OFF + + - name: Build + run: cmake --build build -j$(nproc) + + - name: Test + run: ctest --test-dir build --output-on-failure --timeout 120 + + lint: + name: Verilator Lint + runs-on: ubuntu-latest + + steps: + - name: Checkout + uses: actions/checkout@v4 + + - name: Install Verilator + run: | + sudo apt-get update + sudo apt-get install -y verilator + + - name: Lint RTL + run: | + verilator --lint-only --sv -Wall \ + -Irtl/core/include \ + rtl/soc/richard_soc.sv \ + $(find rtl -name '*.sv' ! -name 'richard_soc.sv') \ + || echo "Lint completed with warnings" diff --git a/rv64cpu/.gitignore b/rv64cpu/.gitignore new file mode 100644 index 0000000..e5b9664 --- /dev/null +++ b/rv64cpu/.gitignore @@ -0,0 +1,30 @@ +# Build +build/ +build_*/ + +# Waves +waves/*.vcd +waves/*.fst + +# IDE +.vscode/ +.idea/ +*.swp +*.swo +*~ + +# Verilator +obj_dir/ + +# FPGA +fpga/xilinx/*.bit +fpga/xilinx/*.ltx +fpga/xilinx/.Xil/ +fpga/xilinx/*.jou +fpga/xilinx/*.log +fpga/xilinx/vivado_proj/ +fpga/gowin/*.fs + +# OS +.DS_Store +Thumbs.db diff --git a/rv64cpu/CMakeLists.txt b/rv64cpu/CMakeLists.txt new file mode 100644 index 0000000..1242a58 --- /dev/null +++ b/rv64cpu/CMakeLists.txt @@ -0,0 +1,72 @@ +cmake_minimum_required(VERSION 3.20) +project(richard_cpu + VERSION 0.1.0 + DESCRIPTION "RV64IMAZicsr_Zifencei Five-Stage Pipelined CPU SoC" + LANGUAGES CXX C +) + +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# ─── Options ──────────────────────────────────────────────────────────────────── +option(ENABLE_TRACE "Enable VCD waveform tracing" ON) +option(ENABLE_COVERAGE "Enable code coverage for RTL" OFF) +option(BUILD_SW "Build software targets (requires riscv64 toolchain)" OFF) + +# ─── Locate Verilator ──────────────────────────────────────────────────────────── +find_package(verilator REQUIRED HINTS $ENV{VERILATOR_ROOT}) +message(STATUS "Found Verilator: ${verilator_DIR}") + +# ─── RTL Source Directories ────────────────────────────────────────────────────── +set(RTL_DIR ${CMAKE_SOURCE_DIR}/rtl) +set(RTL_CORE_DIR ${RTL_DIR}/core) +set(RTL_CACHE_DIR ${RTL_DIR}/cache) +set(RTL_BUS_DIR ${RTL_DIR}/bus) +set(RTL_PERIPS_DIR ${RTL_DIR}/perips) +set(RTL_SOC_DIR ${RTL_DIR}/soc) +set(RTL_INCLUDE_DIR ${RTL_CORE_DIR}/include) + +# ─── Common Verilator Flags ────────────────────────────────────────────────────── +set(VERILATOR_COMMON_FLAGS + --sv + -Wall + -Wno-DECLFILENAME + -Wno-UNUSED + --x-initial unique + --x-assign unique +) + +if(ENABLE_TRACE) + list(APPEND VERILATOR_COMMON_FLAGS --trace) + add_compile_definitions(VM_TRACE=1) +endif() + +if(ENABLE_COVERAGE) + list(APPEND VERILATOR_COMMON_FLAGS --coverage) +endif() + +# ─── Include Verilator CMake Helper ────────────────────────────────────────────── +include(${CMAKE_SOURCE_DIR}/tools/verilator.cmake) + +# ─── Waveform Output Directory ────────────────────────────────────────────────── +file(MAKE_DIRECTORY ${CMAKE_SOURCE_DIR}/waves) + +# ─── Testbench Subdirectory ───────────────────────────────────────────────────── +add_subdirectory(tb) + +# ─── Software Subdirectory (optional) ─────────────────────────────────────────── +if(BUILD_SW) + add_subdirectory(sw) +endif() + +# ─── Summary ──────────────────────────────────────────────────────────────────── +message(STATUS "") +message(STATUS "╔══════════════════════════════════════════════╗") +message(STATUS "║ richard-cpu build configuration ║") +message(STATUS "╠══════════════════════════════════════════════╣") +message(STATUS "║ Trace: ${ENABLE_TRACE}") +message(STATUS "║ Coverage: ${ENABLE_COVERAGE}") +message(STATUS "║ Software: ${BUILD_SW}") +message(STATUS "╚══════════════════════════════════════════════╝") +message(STATUS "") diff --git a/rv64cpu/LICENSE b/rv64cpu/LICENSE new file mode 100644 index 0000000..f288702 --- /dev/null +++ b/rv64cpu/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/> + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +<https://www.gnu.org/licenses/>. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +<https://www.gnu.org/licenses/why-not-lgpl.html>. diff --git a/rv64cpu/README.md b/rv64cpu/README.md new file mode 100644 index 0000000..e2b767d --- /dev/null +++ b/rv64cpu/README.md @@ -0,0 +1,124 @@ +# Richard CPU + +**RV64GCZicsr_Zifencei** Five-Stage In-Order Pipelined Processor SoC + +Written in SystemVerilog, simulated with Verilator, targeting official riscv-arch-test compliance. + +## Features + +- **ISA**: RV64IMAFDC + Zicsr + Zifencei (RV64GC) +- **Pipeline**: 5-stage in-order single-issue (IF → ID → EX → MEM → WB) +- **Privilege Levels**: M / S / U tri-mode +- **Virtual Memory**: Sv39 (MMU with TLB + Hardware PTW) +- **Cache**: I-Cache 4KB + D-Cache 4KB (AXI4-Full Burst refill) +- **Bus**: AXI4-Full (Cache) + AXI4-Lite (Peripherals) + auto bridge +- **Peripherals**: CLINT / PLIC / UART 16550 / GPIO / SRAM Controller +- **Debug**: JTAG Debug Transport Module (reserved) +- **FPGA**: Xilinx / Gowin synthesis support (reserved) + +## Quick Start + +### Dependencies + +- [Verilator](https://verilator.org) ≥ 5.0 +- CMake ≥ 3.20 +- C++17 compiler (GCC / Clang) +- [riscv64-unknown-elf-gcc](https://github.com/riscv-collab/riscv-gnu-toolchain) (software compilation, optional) +- [GTKWave](http://gtkwave.sourceforge.net/) (waveform viewer, optional) + +### Build Simulation + +```bash +# Configure (enable waveform tracing) +cmake -B build -DENABLE_TRACE=ON + +# Compile +cmake --build build -j$(nproc) + +# Run all tests +ctest --test-dir build --output-on-failure +``` + +### Build Bare-Metal Programs + +```bash +cmake -B build_sw -DBUILD_SW=ON \ + -DCMAKE_TOOLCHAIN_FILE=tools/toolchain-riscv64.cmake + +cmake --build build_sw -j$(nproc) +``` + +### Run Compliance Tests + +```bash +# Initialize riscv-arch-test submodule +git submodule update --init --recursive + +# Run RV64I test suite +python3 scripts/run_compliance.py --suite rv64i -v +``` + +### View Waveforms + +```bash +./scripts/wave_view.sh # Open latest waveform +./scripts/wave_view.sh waves/soc.vcd # Open specific file +``` + +## Documentation + +| Document | Description | +|---|---| +| [docs/architecture.md](docs/architecture.md) | Microarchitecture design (pipeline, privilege levels, MMU, FPU, cache, bus) | +| [docs/memory_map.md](docs/memory_map.md) | Physical address space and peripheral register layout | +| [docs/isa_support.md](docs/isa_support.md) | ISA instruction implementation status matrix | +| [docs/pipeline_diagram.md](docs/pipeline_diagram.md) | Pipeline timing, inter-stage registers, forwarding/hazards | + +## Project Structure + +``` +richard-cpu/ +├── CMakeLists.txt # Top-level build +├── rtl/ # SystemVerilog RTL +│ ├── core/ # CPU core (pipeline stages + functional units) +│ │ ├── include/ # Global packages (rv64_pkg, csr_pkg) +│ │ ├── mmu/ # MMU (TLB + PTW) +│ │ ├── fpu/ # FPU (F/D extensions) +│ │ └── debug/ # Debug DTM (reserved) +│ ├── cache/ # I-Cache + D-Cache +│ ├── bus/ # AXI4 interconnect + AXI4-Lite bridge +│ ├── perips/ # Peripherals (CLINT/PLIC/UART/GPIO/SRAM) +│ └── soc/ # SoC top-level integration +├── tb/ # Verilator simulation testbench +│ ├── common/ # Common infrastructure +│ ├── unit/ # Unit tests +│ ├── core/ # Core integration tests +│ ├── soc/ # SoC-level simulation +│ └── compliance/ # riscv-arch-test runner +├── sw/ # Software +│ ├── common/ # Startup code + linker script +│ ├── baremetal/ # Bare-metal test programs +│ └── riscv-arch-test/ # Official compliance tests (git submodule) +├── fpga/ # FPGA synthesis +│ ├── xilinx/ # Artix-7 top-level + constraints + Tcl +│ └── gowin/ # (reserved) +├── scripts/ # Helper scripts +├── tools/ # CMake toolchain files +└── docs/ # Design documentation +``` + +## Roadmap + +| Phase | Milestone | +|---|---| +| P1 | RV64I five-stage pipeline + hazard handling | +| P2 | CSR + M/S/U privilege levels + Trap | +| P3 | MMU (Sv39 TLB + PTW) | +| P4 | Cache + AXI4-Full Burst | +| P5 | Peripherals + AXI4-Lite bridge + SoC integration | +| P6 | Pass riscv-arch-test | +| P7 | M/F/D/A/C extensions + FPGA bring-up | + +## License + +[GPLv3](LICENSE) diff --git a/rv64cpu/docs/architecture.md b/rv64cpu/docs/architecture.md new file mode 100644 index 0000000..9df23d4 --- /dev/null +++ b/rv64cpu/docs/architecture.md @@ -0,0 +1,204 @@ +# Microarchitecture Design Document + +## Overview + +| Parameter | Value | +|---|---| +| ISA | RV64GCZicsr_Zifencei (I+M+A+F+D+C) | +| Pipeline | 5-stage in-order single-issue (IF → ID → EX → MEM → WB) | +| Privilege Levels | M / S / U | +| Virtual Memory | Sv39 (39-bit VA, 56-bit PA, three-level page table) | +| Bus | AXI4-Full (Cache) + AXI4-Lite (Peripherals) | +| Cache | I-Cache 4KB + D-Cache 4KB (direct-mapped, upgradeable to set-associative) | +| Debug | JTAG Debug (reserved) | + +--- + +## Pipeline Timing + +``` +Cycle: 1 2 3 4 5 6 7 + ┌─────┬─────┬─────┬─────┬─────┐ +Instr 1 │ IF │ ID │ EX │ MEM │ WB │ + └─────┼─────┼─────┼─────┼─────┼─────┐ +Instr 2 │ IF │ ID │ EX │ MEM │ WB │ + └─────┼─────┼─────┼─────┼─────┼─────┐ +Instr 3 │ IF │ ID │ EX │ MEM │ WB │ + └─────┴─────┴─────┴─────┴─────┘ +``` + +### Stage Functions + +| Stage | Module | Description | +|---|---|---| +| **IF** | `if_stage.sv` | PC generation, iTLB virtual-to-physical translation, I-Cache read, instruction alignment, branch prediction interface | +| **ID** | `id_stage.sv` | Instruction decode (`decoder.sv`), register file read (`regfile.sv`), immediate extension, CSR read, control signal generation | +| **EX** | `ex_stage.sv` | ALU operations (`alu.sv`), branch resolution (`branch_unit.sv`), multiply/divide (`muldiv.sv`), FPU operations (`fpu.sv`), effective address calculation | +| **MEM** | `mem_stage.sv` | dTLB virtual-to-physical translation, D-Cache read/write, load data alignment/sign extension, exception detection | +| **WB** | `wb_stage.sv` | Register file writeback, CSR writeback, final exception/interrupt handling | + +### Hazard Handling (`hazard_unit.sv`) + +| Type | Strategy | +|---|---| +| RAW Data Hazard | EX→EX forwarding, MEM→EX forwarding | +| Load-use | Stall 1 cycle (insert bubble at IF/ID stage) | +| Control Hazard | Static not-taken prediction; branch resolved at EX stage, flush IF/ID on misprediction | +| Structural Hazard | Eliminated by separate I-Cache / D-Cache | +| FPU Long Latency | Stall EX stage until FPU result ready (or multi-cycle EX) | + +--- + +## Privilege Level Architecture + +### Mode Switching + +```mermaid +stateDiagram-v2 + [*] --> M_Mode : Reset + M_Mode --> S_Mode : mret (mstatus.MPP=S) + M_Mode --> U_Mode : mret (mstatus.MPP=U) + S_Mode --> M_Mode : ecall / exception / interrupt (not delegated) + S_Mode --> U_Mode : sret (sstatus.SPP=U) + U_Mode --> S_Mode : ecall / exception / interrupt (delegated) + U_Mode --> M_Mode : ecall / exception / interrupt (not delegated) +``` + +### CSR Register List + +#### M-Mode CSRs +| CSR | Address | Purpose | +|---|---|---| +| `mstatus` | 0x300 | Global status (MIE, MPIE, MPP, FS, etc.) | +| `misa` | 0x301 | ISA capability descriptor (RV64IMAFD) | +| `medeleg` | 0x302 | Exception delegation to S-mode | +| `mideleg` | 0x303 | Interrupt delegation to S-mode | +| `mie` | 0x304 | Interrupt enable | +| `mtvec` | 0x305 | Trap vector base address | +| `mscratch` | 0x340 | M-mode scratch register | +| `mepc` | 0x341 | Exception PC | +| `mcause` | 0x342 | Trap cause | +| `mtval` | 0x343 | Trap value | +| `mip` | 0x344 | Interrupt pending | +| `mcycle` | 0xB00 | Cycle counter | +| `minstret` | 0xB02 | Retired instruction counter | +| `mvendorid` | 0xF11 | Vendor ID | +| `marchid` | 0xF12 | Architecture ID | +| `mimpid` | 0xF13 | Implementation ID | +| `mhartid` | 0xF14 | Hart ID | + +#### S-Mode CSRs +| CSR | Address | Purpose | +|---|---|---| +| `sstatus` | 0x100 | S-mode status (subset of mstatus) | +| `sie` | 0x104 | S-mode interrupt enable | +| `stvec` | 0x105 | S-mode trap vector | +| `sscratch` | 0x140 | S-mode scratch register | +| `sepc` | 0x141 | S-mode exception PC | +| `scause` | 0x142 | S-mode trap cause | +| `stval` | 0x143 | S-mode trap value | +| `sip` | 0x144 | S-mode interrupt pending | +| `satp` | 0x180 | Page table base address + MODE (Sv39) | + +--- + +## MMU (Sv39) + +### Address Translation + +``` +63 39 38 30 29 21 20 12 11 0 +┌──────────┬────────────┬────────────┬────────────┬────────────┐ +│ (sign) │ VPN[2] │ VPN[1] │ VPN[0] │ Offset │ +│ 25 bits │ 9 bits │ 9 bits │ 9 bits │ 12 bits │ +└──────────┴────────────┴────────────┴────────────┴────────────┘ + 39-bit Virtual Address +``` + +- **iTLB** (IF stage): 16-entry fully associative, for instruction fetch virtual-to-physical translation +- **dTLB** (MEM stage): 16-entry fully associative, for Load/Store virtual-to-physical translation +- **PTW** (`ptw.sv`): On TLB miss, hardware walks the three-level page table, reading page table entries via D-Cache +- **sfence.vma**: Flush TLB (all entries or selective by ASID/VPN) + +### Module Organization + +``` +mmu/ +├── mmu_top.sv ← Top-level: arbitrates iTLB/dTLB PTW requests +├── tlb.sv ← Parameterized TLB: ENTRIES, ASSOC, ASID support +└── ptw.sv ← Page Table Walker: three-level lookup state machine +``` + +--- + +## FPU Architecture (F+D Extensions) + +### Module Organization + +``` +rtl/core/fpu/ +├── fpu_top.sv ← FPU top-level (dispatch + result selection) +├── fp_regfile.sv ← Floating-point register file f0-f31 (64-bit) +├── fp_add.sv ← Addition/subtraction unit +├── fp_mul.sv ← Multiplication unit +├── fp_div_sqrt.sv ← Division/square root (multi-cycle) +├── fp_fma.sv ← Fused multiply-add (optional, high performance) +├── fp_conv.sv ← Format conversion (int↔fp, f32↔f64) +├── fp_cmp.sv ← Compare/classify (FEQ/FLT/FLE/FCLASS) +└── include/ + └── fp_pkg.sv ← Floating-point types, rounding modes, exception flags +``` + +> **Note**: FPU operations typically require multiple cycles (especially division/square root), requiring FPU long-latency stall handling in hazard_unit. CSRs `fcsr` / `frm` / `fflags` are implemented in `csr_unit.sv`. + +--- + +## Cache Subsystem + +See [memory_map.md](memory_map.md) for address mapping. + +| Parameter | I-Cache | D-Cache | +|---|---|---| +| Capacity | 4 KB | 4 KB | +| Line Size | 64 B (8 × 64-bit) | 64 B | +| Associativity | Direct-mapped (initial) | Direct-mapped (initial) | +| Write Policy | N/A | Write-back + write-allocate | +| Refill Bus | AXI4-Full Burst | AXI4-Full Burst | + +### Cache Line Calculation + +- 4 KB / 64 B = 64 lines +- Tag = PA[55:12], Index = PA[11:6], Offset = PA[5:0] + +--- + +## Bus Interconnect + +``` +┌────────────────┐ ┌────────────────┐ +│ I-Cache │ │ D-Cache │ +│ AXI4 Master │ │ AXI4 Master │ +└───────┬────────┘ └───────┬────────┘ + │ │ + └──────┐ ┌──────────┘ + ▼ ▼ + ┌──────────────┐ + │ AXI4 Arbiter │ + └──────┬───────┘ + ▼ + ┌──────────────┐ + │ AXI4 Xbar │ ← Address decode + └──┬───┬───┬───┘ + │ │ │ + ┌──────┘ │ └──────┐ + ▼ ▼ ▼ +┌───────┐ ┌───────────┐ ┌─────────────────┐ +│ SRAM │ │AXI4→Lite │ │ (Expandable │ +│ Ctrl │ │ Bridge │ │ Slave) │ +└───────┘ └─────┬─────┘ └─────────────────┘ + │ + ┌───┬───┴───┬───┐ + ▼ ▼ ▼ ▼ + CLINT PLIC UART GPIO + (AXI4-Lite Slaves) +``` diff --git a/rv64cpu/docs/isa_support.md b/rv64cpu/docs/isa_support.md new file mode 100644 index 0000000..e56eac6 --- /dev/null +++ b/rv64cpu/docs/isa_support.md @@ -0,0 +1,200 @@ +# ISA Support Matrix + +## Target ISA String + +``` +RV64GCZicsr_Zifencei +``` + +Equivalent to `RV64IMAFDCZicsr_Zifencei` + +--- + +## Extension Implementation Status + +| Extension | Full Name | Status | Description | +|---|---|---|---| +| **I** | Base Integer (RV64I) | 🔴 Not implemented | 64-bit base integer instruction set | +| **M** | Multiply/Divide | 🔴 Not implemented | Multiply, divide, remainder | +| **A** | Atomic | 🔴 Not implemented | LR/SC, AMO atomic instructions | +| **F** | Single-Precision Float | 🔴 Not implemented | 32-bit IEEE 754 floating-point | +| **D** | Double-Precision Float | 🔴 Not implemented | 64-bit IEEE 754 floating-point | +| **C** | Compressed | 🔴 Not implemented | 16-bit compressed instructions | +| **Zicsr** | CSR Instructions | 🔴 Not implemented | CSRRW/CSRRS/CSRRC/CSRRWI/CSRRSI/CSRRCI | +| **Zifencei** | Instruction Fence | 🔴 Not implemented | FENCE.I instruction | + +--- + +## RV64I Instruction List + +### R-type Arithmetic/Logic +| Instruction | Operation | Status | +|---|---|---| +| ADD | rd = rs1 + rs2 | ⬜ | +| SUB | rd = rs1 - rs2 | ⬜ | +| AND | rd = rs1 & rs2 | ⬜ | +| OR | rd = rs1 \| rs2 | ⬜ | +| XOR | rd = rs1 ^ rs2 | ⬜ | +| SLL | rd = rs1 << rs2[5:0] | ⬜ | +| SRL | rd = rs1 >> rs2[5:0] (logical) | ⬜ | +| SRA | rd = rs1 >> rs2[5:0] (arith) | ⬜ | +| SLT | rd = (rs1 < rs2) ? 1 : 0 (signed) | ⬜ | +| SLTU | rd = (rs1 < rs2) ? 1 : 0 (unsigned) | ⬜ | + +### R-type RV64 Word Operations +| Instruction | Operation | Status | +|---|---|---| +| ADDW | rd = sext((rs1+rs2)[31:0]) | ⬜ | +| SUBW | rd = sext((rs1-rs2)[31:0]) | ⬜ | +| SLLW | rd = sext((rs1 << rs2[4:0])[31:0]) | ⬜ | +| SRLW | rd = sext((rs1[31:0] >> rs2[4:0])) | ⬜ | +| SRAW | rd = sext((rs1[31:0] >>> rs2[4:0])) | ⬜ | + +### I-type Immediate Arithmetic +| Instruction | Operation | Status | +|---|---|---| +| ADDI | rd = rs1 + imm | ⬜ | +| ANDI | rd = rs1 & imm | ⬜ | +| ORI | rd = rs1 \| imm | ⬜ | +| XORI | rd = rs1 ^ imm | ⬜ | +| SLLI | rd = rs1 << shamt[5:0] | ⬜ | +| SRLI | rd = rs1 >> shamt[5:0] (logical) | ⬜ | +| SRAI | rd = rs1 >> shamt[5:0] (arith) | ⬜ | +| SLTI | rd = (rs1 < imm) ? 1 : 0 (signed) | ⬜ | +| SLTIU | rd = (rs1 < imm) ? 1 : 0 (unsigned) | ⬜ | +| ADDIW | rd = sext((rs1+imm)[31:0]) | ⬜ | +| SLLIW | rd = sext((rs1 << shamt[4:0])[31:0]) | ⬜ | +| SRLIW | rd = sext((rs1[31:0] >> shamt[4:0])) | ⬜ | +| SRAIW | rd = sext((rs1[31:0] >>> shamt[4:0])) | ⬜ | + +### Load +| Instruction | Width | Sign Extension | Status | +|---|---|---|---| +| LB | 8-bit | Signed | ⬜ | +| LBU | 8-bit | Zero-extended | ⬜ | +| LH | 16-bit | Signed | ⬜ | +| LHU | 16-bit | Zero-extended | ⬜ | +| LW | 32-bit | Signed | ⬜ | +| LWU | 32-bit | Zero-extended | ⬜ | +| LD | 64-bit | — | ⬜ | + +### Store +| Instruction | Width | Status | +|---|---|---| +| SB | 8-bit | ⬜ | +| SH | 16-bit | ⬜ | +| SW | 32-bit | ⬜ | +| SD | 64-bit | ⬜ | + +### Branch +| Instruction | Condition | Status | +|---|---|---| +| BEQ | rs1 == rs2 | ⬜ | +| BNE | rs1 != rs2 | ⬜ | +| BLT | rs1 < rs2 (signed) | ⬜ | +| BGE | rs1 >= rs2 (signed) | ⬜ | +| BLTU | rs1 < rs2 (unsigned) | ⬜ | +| BGEU | rs1 >= rs2 (unsigned) | ⬜ | + +### Upper Immediate / Jump +| Instruction | Operation | Status | +|---|---|---| +| LUI | rd = imm << 12 | ⬜ | +| AUIPC | rd = pc + (imm << 12) | ⬜ | +| JAL | rd = pc+4; pc = pc + imm | ⬜ | +| JALR | rd = pc+4; pc = (rs1 + imm) & ~1 | ⬜ | + +### System +| Instruction | Status | +|---|---| +| ECALL | ⬜ | +| EBREAK | ⬜ | +| MRET | ⬜ | +| SRET | ⬜ | +| WFI | ⬜ | +| FENCE | ⬜ | +| FENCE.I | ⬜ | +| SFENCE.VMA | ⬜ | + +--- + +## M Extension (Multiply/Divide) + +| Instruction | Operation | Status | +|---|---|---| +| MUL | rd = (rs1 × rs2)[63:0] | ⬜ | +| MULH | rd = (rs1 × rs2)[127:64] signed | ⬜ | +| MULHSU | rd = (rs1 × rs2)[127:64] signed×unsigned | ⬜ | +| MULHU | rd = (rs1 × rs2)[127:64] unsigned | ⬜ | +| DIV | rd = rs1 / rs2 signed | ⬜ | +| DIVU | rd = rs1 / rs2 unsigned | ⬜ | +| REM | rd = rs1 % rs2 signed | ⬜ | +| REMU | rd = rs1 % rs2 unsigned | ⬜ | +| MULW | rd = sext((rs1×rs2)[31:0]) | ⬜ | +| DIVW / DIVUW | 32-bit division | ⬜ | +| REMW / REMUW | 32-bit remainder | ⬜ | + +--- + +## A Extension (Atomic Instructions) + +| Instruction | Status | +|---|---| +| LR.W / LR.D | ⬜ | +| SC.W / SC.D | ⬜ | +| AMOSWAP.W/D | ⬜ | +| AMOADD.W/D | ⬜ | +| AMOAND.W/D | ⬜ | +| AMOOR.W/D | ⬜ | +| AMOXOR.W/D | ⬜ | +| AMOMAX[U].W/D | ⬜ | +| AMOMIN[U].W/D | ⬜ | + +--- + +## F/D Extension (Floating-Point) + +| Category | F (32-bit) Instructions | D (64-bit) Instructions | Status | +|---|---|---|---| +| Load/Store | FLW, FSW | FLD, FSD | ⬜ | +| Arithmetic | FADD.S, FSUB.S, FMUL.S, FDIV.S, FSQRT.S | FADD.D, ... | ⬜ | +| Fused Multiply-Add | FMADD.S, FMSUB.S, FNMADD.S, FNMSUB.S | FMADD.D, ... | ⬜ | +| Sign Manipulation | FSGNJ[N/X].S | FSGNJ[N/X].D | ⬜ | +| Compare | FEQ.S, FLT.S, FLE.S | FEQ.D, FLT.D, FLE.D | ⬜ | +| Classify | FCLASS.S | FCLASS.D | ⬜ | +| Conversion | FCVT.W/WU/L/LU.S, FCVT.S.W/WU/L/LU | FCVT.*.D | ⬜ | +| F↔D Conversion | — | FCVT.S.D, FCVT.D.S | ⬜ | +| Move | FMV.X.W, FMV.W.X | FMV.X.D, FMV.D.X | ⬜ | +| MIN/MAX | FMIN.S, FMAX.S | FMIN.D, FMAX.D | ⬜ | + +### Floating-Point CSRs +| CSR | Address | Description | +|---|---|---| +| `fflags` | 0x001 | Floating-point exception flags (NV, DZ, OF, UF, NX) | +| `frm` | 0x002 | Floating-point rounding mode | +| `fcsr` | 0x003 | fflags + frm combined | + +--- + +## C Extension (Compressed Instructions) + +16-bit encoded subset of common instructions, improving code density. Requires handling 16/32-bit mixed instruction stream alignment at the IF stage. + +| Quadrant | Selected Instructions | Status | +|---|---|---| +| C0 | C.LW, C.LD, C.SW, C.SD, C.ADDI4SPN | ⬜ | +| C1 | C.ADDI, C.LI, C.LUI, C.SRLI, C.SRAI, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.J, C.BEQZ, C.BNEZ | ⬜ | +| C2 | C.SLLI, C.LDSP, C.LWSP, C.JR, C.MV, C.JALR, C.ADD, C.SDSP, C.SWSP | ⬜ | + +--- + +## Zicsr Instructions + +| Instruction | Operation | Status | +|---|---|---| +| CSRRW | t=CSR; CSR=rs1; rd=t | ⬜ | +| CSRRS | t=CSR; CSR=t\|rs1; rd=t | ⬜ | +| CSRRC | t=CSR; CSR=t&~rs1; rd=t | ⬜ | +| CSRRWI | t=CSR; CSR=zimm; rd=t | ⬜ | +| CSRRSI | t=CSR; CSR=t\|zimm; rd=t | ⬜ | +| CSRRCI | t=CSR; CSR=t&~zimm; rd=t | ⬜ | diff --git a/rv64cpu/docs/memory_map.md b/rv64cpu/docs/memory_map.md new file mode 100644 index 0000000..9bf529b --- /dev/null +++ b/rv64cpu/docs/memory_map.md @@ -0,0 +1,113 @@ +# Memory Map + +## Physical Address Space + +``` +0xFFFF_FFFF_FFFF_FFFF ┌─────────────────────────┐ + │ │ + │ (unused) │ + │ │ +0x0000_0000_1000_2000 ├─────────────────────────┤ + │ GPIO 4 KB │ +0x0000_0000_1000_1000 ├─────────────────────────┤ + │ UART0 4 KB │ +0x0000_0000_1000_0000 ├─────────────────────────┤ + │ │ + │ (unused) │ + │ │ +0x0000_0000_0C00_0000 ├─────────────────────────┤ + │ PLIC 64 MB │ +0x0000_0000_0BFF_FFFF ├─────────────────────────┤ + │ │ + │ (unused) │ + │ │ +0x0000_0000_0200_FFFF ├─────────────────────────┤ + │ CLINT 64 KB │ +0x0000_0000_0200_0000 ├─────────────────────────┤ + │ │ + │ (unused) │ + │ │ +0x0000_0000_0FFF_FFFF ├─────────────────────────┤ + │ │ + │ SRAM / RAM ~256 MB │ + │ (Boot ROM at lowest │ + │ 64KB) │ + │ │ +0x0000_0000_0000_0000 └─────────────────────────┘ +``` + +## Address Decode Table + +| Start Address | End Address | Size | Peripheral | Bus | Description | +|---|---|---|---|---|---| +| `0x0000_0000` | `0x0FFF_FFFF` | 256 MB | SRAM Controller | AXI4-Full | Boot ROM (0x0~0xFFFF) + RAM | +| `0x0200_0000` | `0x0200_FFFF` | 64 KB | CLINT | AXI4-Lite | mtime, mtimecmp, MSIP | +| `0x0C00_0000` | `0x0FFF_FFFF` | 64 MB | PLIC | AXI4-Lite | External interrupt controller | +| `0x1000_0000` | `0x1000_0FFF` | 4 KB | UART0 | AXI4-Lite | 16550 compatible | +| `0x1000_1000` | `0x1000_1FFF` | 4 KB | GPIO | AXI4-Lite | General-purpose I/O | + +> **Note**: The address ranges for CLINT and PLIC follow the RISC-V community recommended layout, compatible with Linux/OpenSBI. + +## CLINT Register Layout + +| Offset | Register | Description | +|---|---|---| +| `0x0000` | `msip[0]` | Machine software interrupt pending | +| `0x4000` | `mtimecmp[0]` | Machine timer compare value (64-bit) | +| `0xBFF8` | `mtime` | Machine timer current value (64-bit) | + +## PLIC Register Layout (Simplified) + +| Offset | Register | Description | +|---|---|---| +| `0x000000` | `priority[1..N]` | Interrupt source priority | +| `0x001000` | `pending[0..N/32]` | Interrupt pending bitfield | +| `0x002000` | `enable[ctx][0..N/32]` | Interrupt enable bitfield | +| `0x200000` | `threshold[ctx]` | Priority threshold | +| `0x200004` | `claim/complete[ctx]` | Interrupt claim/complete | + +## UART0 Register Layout (16550) + +| Offset | Register | Read/Write | Description | +|---|---|---|---| +| `0x00` | RBR / THR | R / W | Receive/transmit data | +| `0x01` | IER | R/W | Interrupt enable | +| `0x02` | IIR / FCR | R / W | Interrupt identification / FIFO control | +| `0x03` | LCR | R/W | Line control | +| `0x05` | LSR | R | Line status | + +## Linker Script Correspondence + +The MEMORY regions in `sw/common/link.ld` correspond to this table: +- `ROM`: `0x0000_0000`, 64 KB +- `RAM`: `0x0001_0000`, 256 MB - 64 KB + +## Address Decode Implementation + +The address decode logic in RTL is located in `rtl/soc/mem_map.sv` and `rtl/bus/axi4_xbar.sv`. + +Constants are defined in `mem_map.sv`: + +```systemverilog +package mem_map_pkg; + // SRAM + localparam logic [63:0] SRAM_BASE = 64'h0000_0000; + localparam logic [63:0] SRAM_SIZE = 64'h1000_0000; // 256 MB + + // CLINT + localparam logic [63:0] CLINT_BASE = 64'h0200_0000; + localparam logic [63:0] CLINT_SIZE = 64'h0001_0000; // 64 KB + + // PLIC + localparam logic [63:0] PLIC_BASE = 64'h0C00_0000; + localparam logic [63:0] PLIC_SIZE = 64'h0400_0000; // 64 MB + + // UART0 + localparam logic [63:0] UART0_BASE = 64'h1000_0000; + localparam logic [63:0] UART0_SIZE = 64'h0000_1000; // 4 KB + + // GPIO + localparam logic [63:0] GPIO_BASE = 64'h1000_1000; + localparam logic [63:0] GPIO_SIZE = 64'h0000_1000; // 4 KB +endpackage +``` diff --git a/rv64cpu/docs/pipeline_diagram.md b/rv64cpu/docs/pipeline_diagram.md new file mode 100644 index 0000000..e2f6bdb --- /dev/null +++ b/rv64cpu/docs/pipeline_diagram.md @@ -0,0 +1,156 @@ +# Pipeline Timing and Datapath + +## Five-Stage Pipeline Datapath + +``` + ┌────────────────────────────────────────────────────────────────┐ + │ HAZARD UNIT │ + │ Forward A/B, Stall, Flush, FPU interlock │ + └──┬─────────┬──────────┬──────────┬──────────┬────────────────┘ + │ │ │ │ │ + ┌─────▼──┐ ┌───▼───┐ ┌────▼───┐ ┌───▼────┐ ┌──▼─────┐ + │ IF │ │ ID │ │ EX │ │ MEM │ │ WB │ + │ │ │ │ │ │ │ │ │ │ + ┌──────┐ │ PC Gen │ │Decode │ │ ALU │ │D-Cache │ │ Write │ + │ iTLB ├───►│ ↓ │ │ ↓ │ │ Branch │ │ LSU │ │ Back │ + │ │ │I-Cache │ │RegFile│ │ MulDiv │ │ dTLB │ │ │ + └──────┘ │ Fetch │ │ Read │ │ FPU │ │ │ │ │ + │ │ │ ImmEx │ │ │ │ │ │ │ + └───┬────┘ └───┬───┘ └────┬───┘ └───┬────┘ └───┬────┘ + │ │ │ │ │ + ┌───▼──────────▼──┐ ┌─────▼──────────▼──┐ ┌────▼─────┐ + │ IF/ID Reg │ │ EX/MEM Reg │ │ MEM/WB │ + │ │ │ │ │ Reg │ + └────────────────┘ └────────────────────┘ └──────────┘ + ↑ + ┌───────┴───────┐ + │ CSR Unit │ + │ Trap Ctrl │ + └───────────────┘ +``` + +--- + +## Inter-Stage Registers + +### IF/ID Register + +| Field | Width | Description | +|---|---|---| +| `pc` | 64 | Current instruction PC | +| `instr` | 32 | Fetched instruction | +| `valid` | 1 | Instruction valid | +| `exception` | 1 | IF stage exception (e.g., instruction page fault) | +| `exc_code` | 4 | Exception code | +| `predicted_taken` | 1 | Branch prediction result | +| `predicted_target` | 64 | Predicted target address | + +### ID/EX Register + +| Field | Width | Description | +|---|---|---| +| `pc` | 64 | | +| `rs1_data` | 64 | Register source 1 value | +| `rs2_data` | 64 | Register source 2 value | +| `rs3_data` | 64 | FPU source 3 value (FMA) | +| `imm` | 64 | Sign-extended immediate | +| `rd_addr` | 5 | Destination register address | +| `rs1_addr` | 5 | Source 1 address (for forwarding) | +| `rs2_addr` | 5 | Source 2 address (for forwarding) | +| `ctrl` | struct | Control signal bundle (ALU op, mem r/w, branch type, etc.) | +| `valid` | 1 | | +| `is_fp` | 1 | Floating-point instruction flag | + +### EX/MEM Register + +| Field | Width | Description | +|---|---|---| +| `pc` | 64 | | +| `alu_result` | 64 | ALU/FPU computation result | +| `rs2_data` | 64 | Store data | +| `rd_addr` | 5 | | +| `ctrl_mem` | struct | Memory access control (read/write, size, sign_ext) | +| `ctrl_wb` | struct | Writeback control (reg_write, wb_sel) | +| `valid` | 1 | | + +### MEM/WB Register + +| Field | Width | Description | +|---|---|---| +| `pc` | 64 | | +| `alu_result` | 64 | | +| `mem_data` | 64 | Data read from D-Cache | +| `rd_addr` | 5 | | +| `ctrl_wb` | struct | Writeback control | +| `valid` | 1 | | + +--- + +## Forwarding Paths + +``` + EX Stage MEM Stage WB Stage + ┌────────┐ ┌─────────┐ ┌────────┐ + │ ALU │ │alu_result│ │ wb_data│ + │ result ├────────┐ │ or ├────────┐ │ │ + └────────┘ │ │ mem_data │ │ └────┬───┘ + │ └─────────┘ │ │ + ┌─────▼──────────────────────▼────────▼─┐ + │ Forward MUX │ + │ sel = hazard_unit.forward_a/b │ + └─────────────────┬─────────────────────┘ + │ + ▼ + EX Stage rs1/rs2 input +``` + +| Forwarding Source | Condition | +|---|---| +| EX→EX | `ex_mem.rd == id_ex.rs1/rs2` and `ex_mem.reg_write` | +| MEM→EX | `mem_wb.rd == id_ex.rs1/rs2` and `mem_wb.reg_write` and no EX forwarding | +| Load-use | `id_ex.mem_read` and `id_ex.rd == if_id.rs1/rs2` → **stall** | + +--- + +## Branch Handling Timing + +``` +Cycle: 1 2 3 4 5 + ┌─────┬─────┬─────┬─────┬─────┐ +Branch │ IF │ ID │ EX │ MEM │ WB │ ← Branch resolved at EX stage + └─────┼─────┼─────┼─────┼─────┘ +Instr+1 │ IF │ ID │ ██ │ ← Misprediction: flush (2-cycle penalty) + └─────┼─────┼─────┘ +Instr+2 │ IF │ ██ │ ← flush + └─────┴─────┘ +Target │ IF │ ID │ EX │ ... ← Correct path begins + └─────┴─────┴─────┘ +``` + +--- + +## Cache Miss Timing + +``` +Cycle: 1 2 3 4 5 6 7 8 ... N N+1 + ┌────┬────┬────┬────────────────────────────┬────┬────┐ +Instr │ IF │ ID │ EX │ MEM (D-Cache MISS) │ │ WB │ + └────┴────┴────┤ Stall pipeline... ├────┴────┘ + │ AXI4 Burst read (8 beats)│ + │ Fill cache line │ + └─────────────────────────────┘ +``` + +--- + +## TLB Miss → PTW Timing + +``` +Cycle: 1 2 3 ... N N+1 N+2 + ┌────┬────────────────────────┬────┬────┐ +Instr │ IF │ iTLB MISS → PTW walk │ IF │ ID │ ... + └────┤ (3-level page table ├────┴────┘ + │ × memory latency) │ + │ Pipeline stalled │ + └────────────────────────┘ +``` diff --git a/rv64cpu/fpga/gowin/.gitkeep b/rv64cpu/fpga/gowin/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/fpga/gowin/.gitkeep diff --git a/rv64cpu/fpga/xilinx/.gitkeep b/rv64cpu/fpga/xilinx/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/fpga/xilinx/.gitkeep diff --git a/rv64cpu/rtl/bus/.gitkeep b/rv64cpu/rtl/bus/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/bus/.gitkeep diff --git a/rv64cpu/rtl/cache/.gitkeep b/rv64cpu/rtl/cache/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/cache/.gitkeep diff --git a/rv64cpu/rtl/core/.gitkeep b/rv64cpu/rtl/core/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/core/.gitkeep diff --git a/rv64cpu/rtl/core/debug/.gitkeep b/rv64cpu/rtl/core/debug/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/core/debug/.gitkeep diff --git a/rv64cpu/rtl/core/fpu/.gitkeep b/rv64cpu/rtl/core/fpu/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/core/fpu/.gitkeep diff --git a/rv64cpu/rtl/core/fpu/include/.gitkeep b/rv64cpu/rtl/core/fpu/include/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/core/fpu/include/.gitkeep diff --git a/rv64cpu/rtl/core/include/.gitkeep b/rv64cpu/rtl/core/include/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/core/include/.gitkeep diff --git a/rv64cpu/rtl/core/mmu/.gitkeep b/rv64cpu/rtl/core/mmu/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/core/mmu/.gitkeep diff --git a/rv64cpu/rtl/perips/.gitkeep b/rv64cpu/rtl/perips/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/perips/.gitkeep diff --git a/rv64cpu/rtl/soc/.gitkeep b/rv64cpu/rtl/soc/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/rtl/soc/.gitkeep diff --git a/rv64cpu/scripts/.gitkeep b/rv64cpu/scripts/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/scripts/.gitkeep diff --git a/rv64cpu/scripts/gen_hex.sh b/rv64cpu/scripts/gen_hex.sh new file mode 100755 index 0000000..8ba4c94 --- /dev/null +++ b/rv64cpu/scripts/gen_hex.sh @@ -0,0 +1,25 @@ +#!/usr/bin/env bash +# ─── gen_hex.sh ────────────────────────────────────────────────────────────────── +# Convert an ELF file to Verilog hex format for $readmemh +# +# Usage: ./scripts/gen_hex.sh <input.elf> [output.hex] +# ───────────────────────────────────────────────────────────────────────────────── +set -euo pipefail + +CROSS_PREFIX="${CROSS_PREFIX:-riscv64-unknown-elf-}" + +if [ $# -lt 1 ]; then + echo "Usage: $0 <input.elf> [output.hex]" + exit 1 +fi + +INPUT="$1" +OUTPUT="${2:-${INPUT%.elf}.hex}" + +${CROSS_PREFIX}objcopy -O verilog "$INPUT" "$OUTPUT" +echo "[gen_hex] $INPUT → $OUTPUT" + +# Also generate .bin and disassembly for inspection +${CROSS_PREFIX}objcopy -O binary "$INPUT" "${INPUT%.elf}.bin" +${CROSS_PREFIX}objdump -d -M no-aliases "$INPUT" > "${INPUT%.elf}.dump" +echo "[gen_hex] Also generated .bin and .dump" diff --git a/rv64cpu/scripts/run_compliance.py b/rv64cpu/scripts/run_compliance.py new file mode 100755 index 0000000..92456ec --- /dev/null +++ b/rv64cpu/scripts/run_compliance.py @@ -0,0 +1,120 @@ +#!/usr/bin/env python3 +""" +run_compliance.py — riscv-arch-test 自动化运行脚本 + +Usage: + python3 scripts/run_compliance.py --suite rv64i + python3 scripts/run_compliance.py --suite rv64im --build-dir build + python3 scripts/run_compliance.py --list + +Requirements: + - Verilator simulation binary built (tb_soc or compliance_runner) + - riscv64-unknown-elf-gcc toolchain in PATH + - sw/riscv-arch-test submodule initialized +""" + +import argparse +import subprocess +import sys +import os +from pathlib import Path + +PROJECT_ROOT = Path(__file__).resolve().parent.parent +ARCH_TEST_DIR = PROJECT_ROOT / "sw" / "riscv-arch-test" +BUILD_DIR = PROJECT_ROOT / "build" + +SUITES = { + "rv64i": "riscv-test-suite/rv64i_m/I", + "rv64im": "riscv-test-suite/rv64i_m/M", + "rv64ia": "riscv-test-suite/rv64i_m/A", + "rv64if": "riscv-test-suite/rv64i_m/F", + "rv64id": "riscv-test-suite/rv64i_m/D", + "rv64ic": "riscv-test-suite/rv64i_m/C", + "rv64priv": "riscv-test-suite/rv64i_m/privilege", +} + + +def list_suites(): + print("Available test suites:") + for name, path in SUITES.items(): + exists = "✓" if (ARCH_TEST_DIR / path).exists() else "✗ (not found)" + print(f" {name:12s} → {path} {exists}") + + +def run_suite(suite_name: str, build_dir: Path, sim_binary: str, verbose: bool): + if suite_name not in SUITES: + print(f"Unknown suite: {suite_name}") + print(f"Available: {', '.join(SUITES.keys())}") + sys.exit(1) + + suite_path = ARCH_TEST_DIR / SUITES[suite_name] + if not suite_path.exists(): + print(f"Suite path not found: {suite_path}") + print("Did you initialize the submodule?") + print(" git submodule update --init --recursive") + sys.exit(1) + + sim_bin = build_dir / sim_binary + if not sim_bin.exists(): + print(f"Simulation binary not found: {sim_bin}") + print("Build it first: cmake --build build --target compliance_runner") + sys.exit(1) + + test_files = sorted(suite_path.glob("src/*.S")) + if not test_files: + print(f"No test sources found in {suite_path / 'src'}") + sys.exit(1) + + print(f"\n{'='*60}") + print(f"Running {suite_name} compliance tests ({len(test_files)} tests)") + print(f"{'='*60}\n") + + passed = 0 + failed = 0 + errors = [] + + for test_file in test_files: + test_name = test_file.stem + if verbose: + print(f" [{test_name}] ", end="", flush=True) + + # TODO: Implement actual test compilation and simulation + # This is a skeleton — fill in with your specific flow: + # 1. Compile test_file with riscv64-unknown-elf-gcc + # 2. Run the sim binary with the compiled ELF + # 3. Compare signature output against reference + if verbose: + print("⏭ SKIP (runner not yet implemented)") + + print(f"\n{'='*60}") + print(f"Results: {passed} passed, {failed} failed, {len(test_files) - passed - failed} skipped") + print(f"{'='*60}\n") + + return failed == 0 + + +def main(): + parser = argparse.ArgumentParser(description="Run riscv-arch-test compliance tests") + parser.add_argument("--suite", type=str, help="Test suite to run") + parser.add_argument("--build-dir", type=str, default="build", help="Build directory") + parser.add_argument("--sim", type=str, default="compliance_runner", help="Sim binary name") + parser.add_argument("--list", action="store_true", help="List available suites") + parser.add_argument("-v", "--verbose", action="store_true", help="Verbose output") + + args = parser.parse_args() + + if args.list: + list_suites() + return + + if not args.suite: + parser.print_help() + sys.exit(1) + + build_dir = Path(args.build_dir) + success = run_suite(args.suite, build_dir, args.sim, args.verbose) + sys.exit(0 if success else 1) + + +if __name__ == "__main__": + main() diff --git a/rv64cpu/scripts/wave_view.sh b/rv64cpu/scripts/wave_view.sh new file mode 100755 index 0000000..5a3a6e4 --- /dev/null +++ b/rv64cpu/scripts/wave_view.sh @@ -0,0 +1,25 @@ +#!/usr/bin/env bash +# ─── wave_view.sh ──────────────────────────────────────────────────────────────── +# Open a VCD/FST waveform file in GTKWave +# +# Usage: ./scripts/wave_view.sh [waveform_file] +# ./scripts/wave_view.sh # opens latest .vcd in waves/ +# ───────────────────────────────────────────────────────────────────────────────── +set -euo pipefail + +WAVES_DIR="$(dirname "$0")/../waves" +VIEWER="${WAVE_VIEWER:-gtkwave}" + +if [ $# -ge 1 ]; then + WAVE_FILE="$1" +else + # Open the most recently modified waveform file + WAVE_FILE=$(ls -t "$WAVES_DIR"/*.vcd "$WAVES_DIR"/*.fst 2>/dev/null | head -1) + if [ -z "$WAVE_FILE" ]; then + echo "No waveform files found in $WAVES_DIR" + exit 1 + fi +fi + +echo "[wave_view] Opening: $WAVE_FILE" +$VIEWER "$WAVE_FILE" & diff --git a/rv64cpu/sw/CMakeLists.txt b/rv64cpu/sw/CMakeLists.txt new file mode 100644 index 0000000..c43580f --- /dev/null +++ b/rv64cpu/sw/CMakeLists.txt @@ -0,0 +1,71 @@ +# ─── Software Build (Bare-Metal) ───────────────────────────────────────────────── +# +# This CMakeLists.txt is only included when BUILD_SW=ON and requires +# the RISC-V cross-compilation toolchain: +# +# cmake -B build_sw -DBUILD_SW=ON \ +# -DCMAKE_TOOLCHAIN_FILE=tools/toolchain-riscv64.cmake +# +# ───────────────────────────────────────────────────────────────────────────────── + +enable_language(ASM) + +set(LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/common/link.ld) +set(STARTUP_SRC ${CMAKE_CURRENT_SOURCE_DIR}/common/start.S) + +# ─── Helper: create a bare-metal firmware target ───────────────────────────────── +function(add_firmware) + cmake_parse_arguments(FW "" "NAME" "SOURCES" ${ARGN}) + + add_executable(${FW_NAME}.elf + ${STARTUP_SRC} + ${FW_SOURCES} + ) + + target_include_directories(${FW_NAME}.elf PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/common + ) + + target_link_options(${FW_NAME}.elf PRIVATE + -T${LINKER_SCRIPT} + -Wl,-Map=${FW_NAME}.map + ) + + # Generate .bin + add_custom_command(TARGET ${FW_NAME}.elf POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O binary + ${FW_NAME}.elf ${FW_NAME}.bin + COMMENT "Generating ${FW_NAME}.bin" + ) + + # Generate .hex (for $readmemh) + add_custom_command(TARGET ${FW_NAME}.elf POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O verilog + ${FW_NAME}.elf ${FW_NAME}.hex + COMMENT "Generating ${FW_NAME}.hex" + ) + + # Print size + add_custom_command(TARGET ${FW_NAME}.elf POST_BUILD + COMMAND ${CMAKE_SIZE} ${FW_NAME}.elf + ) +endfunction() + +# ═══════════════════════════════════════════════════════════════════════════════════ +# Firmware Targets — uncomment as you create the source files +# ═══════════════════════════════════════════════════════════════════════════════════ +# +# add_firmware( +# NAME hello_uart +# SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/baremetal/hello_uart/main.c +# ) +# +# add_firmware( +# NAME timer_irq +# SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/baremetal/timer_irq/main.c +# ) +# +# add_firmware( +# NAME cache_test +# SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/baremetal/cache_test/main.c +# ) diff --git a/rv64cpu/sw/baremetal/cache_test/.gitkeep b/rv64cpu/sw/baremetal/cache_test/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/sw/baremetal/cache_test/.gitkeep diff --git a/rv64cpu/sw/baremetal/hello_uart/.gitkeep b/rv64cpu/sw/baremetal/hello_uart/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/sw/baremetal/hello_uart/.gitkeep diff --git a/rv64cpu/sw/baremetal/timer_irq/.gitkeep b/rv64cpu/sw/baremetal/timer_irq/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/sw/baremetal/timer_irq/.gitkeep diff --git a/rv64cpu/sw/common/.gitkeep b/rv64cpu/sw/common/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/sw/common/.gitkeep diff --git a/rv64cpu/sw/common/link.ld b/rv64cpu/sw/common/link.ld new file mode 100644 index 0000000..705a25d --- /dev/null +++ b/rv64cpu/sw/common/link.ld @@ -0,0 +1,76 @@ +/* ═══════════════════════════════════════════════════════════════════════════════ + * richard-cpu Linker Script + * + * Memory map matches rtl/soc/mem_map.sv + * ═══════════════════════════════════════════════════════════════════════════════ */ + +OUTPUT_ARCH("riscv") +ENTRY(_start) + +MEMORY +{ + /* Boot ROM / SRAM — 256 MB total addressable, practical limit is FPGA BRAM */ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (rwx) : ORIGIN = 0x00010000, LENGTH = 256M - 64K +} + +SECTIONS +{ + /* ── Code ──────────────────────────────────────────────────────────────── */ + .text : ALIGN(4) + { + *(.text.init) /* _start / trap vector MUST be first */ + *(.text .text.*) + } > ROM + + /* ── Read-only data ───────────────────────────────────────────────────── */ + .rodata : ALIGN(8) + { + *(.rodata .rodata.*) + *(.srodata .srodata.*) + } > ROM + + /* ── Initialized data (load from ROM, copy to RAM) ────────────────────── */ + .data : ALIGN(8) + { + _data_start = .; + *(.data .data.*) + *(.sdata .sdata.*) + _data_end = .; + } > RAM AT > ROM + + _data_load = LOADADDR(.data); + + /* ── BSS (zero-initialized) ──────────────────────────────────────────── */ + .bss (NOLOAD) : ALIGN(8) + { + _bss_start = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + *(COMMON) + _bss_end = .; + } > RAM + + /* ── Stack (grows downward) ──────────────────────────────────────────── */ + . = ALIGN(16); + _stack_bottom = .; + . = . + 8K; + _stack_top = .; + + /* ── Heap ────────────────────────────────────────────────────────────── */ + _heap_start = .; + + /* ── tohost / fromhost (Compliance test interface) ────────────────────── */ + .tohost (NOLOAD) : ALIGN(8) + { + PROVIDE(tohost = .); . += 8; + PROVIDE(fromhost = .); . += 8; + } > RAM + + /DISCARD/ : + { + *(.comment) + *(.note.*) + *(.eh_frame*) + } +} diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt new file mode 100644 index 0000000..8679562 --- /dev/null +++ b/rv64cpu/tb/CMakeLists.txt @@ -0,0 +1,99 @@ +# ─── Testbench CMake ────────────────────────────────────────────────────────────── +# +# Each testbench is registered as a Verilator simulation target + CTest. +# +# To add a new unit test, call: +# add_verilator_target( +# NAME tb_<module> +# TOP_MODULE <module> +# SOURCES ${RTL_CORE_DIR}/<module>.sv [... dependencies ...] +# INCLUDE_DIRS ${RTL_INCLUDE_DIR} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_<module>.cpp +# ) +# + +enable_testing() + +# ─── Collect common RTL include dirs ───────────────────────────────────────────── +set(RTL_COMMON_INCLUDES + ${RTL_INCLUDE_DIR} +) + +# ─── Collect all RTL sources for SoC-level sim ─────────────────────────────────── +file(GLOB_RECURSE ALL_RTL_SOURCES + ${RTL_DIR}/*.sv +) + +# ═══════════════════════════════════════════════════════════════════════════════════ +# Unit Tests +# ═══════════════════════════════════════════════════════════════════════════════════ +# +# Uncomment and fill in as you implement each module, for example: +# +# add_verilator_target( +# NAME tb_alu +# TOP_MODULE alu +# SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv +# ${RTL_CORE_DIR}/alu.sv +# INCLUDE_DIRS ${RTL_COMMON_INCLUDES} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_alu.cpp +# ) +# +# add_verilator_target( +# NAME tb_decoder +# TOP_MODULE decoder +# SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv +# ${RTL_CORE_DIR}/decoder.sv +# INCLUDE_DIRS ${RTL_COMMON_INCLUDES} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_decoder.cpp +# ) +# +# add_verilator_target( +# NAME tb_regfile +# TOP_MODULE regfile +# SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv +# ${RTL_CORE_DIR}/regfile.sv +# INCLUDE_DIRS ${RTL_COMMON_INCLUDES} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_regfile.cpp +# ) +# +# add_verilator_target( +# NAME tb_csr +# TOP_MODULE csr_unit +# SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv +# ${RTL_CORE_DIR}/include/csr_pkg.sv +# ${RTL_CORE_DIR}/csr_unit.sv +# INCLUDE_DIRS ${RTL_COMMON_INCLUDES} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_csr.cpp +# ) + +# ═══════════════════════════════════════════════════════════════════════════════════ +# Core Integration Test +# ═══════════════════════════════════════════════════════════════════════════════════ +# +# add_verilator_target( +# NAME tb_core +# TOP_MODULE richard_core +# SOURCES ${ALL_RTL_SOURCES} +# INCLUDE_DIRS ${RTL_COMMON_INCLUDES} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/core/tb_core.cpp +# ) + +# ═══════════════════════════════════════════════════════════════════════════════════ +# SoC Integration Test +# ═══════════════════════════════════════════════════════════════════════════════════ +# +# add_verilator_target( +# NAME tb_soc +# TOP_MODULE richard_soc +# SOURCES ${ALL_RTL_SOURCES} +# INCLUDE_DIRS ${RTL_COMMON_INCLUDES} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/soc/tb_soc.cpp +# EXTRA_FLAGS --threads 2 +# ) + +# ═══════════════════════════════════════════════════════════════════════════════════ +# Compliance Tests +# ═══════════════════════════════════════════════════════════════════════════════════ +# +# add_subdirectory(compliance) diff --git a/rv64cpu/tb/common/.gitkeep b/rv64cpu/tb/common/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/tb/common/.gitkeep diff --git a/rv64cpu/tb/compliance/.gitkeep b/rv64cpu/tb/compliance/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/tb/compliance/.gitkeep diff --git a/rv64cpu/tb/compliance/CMakeLists.txt b/rv64cpu/tb/compliance/CMakeLists.txt new file mode 100644 index 0000000..b832f01 --- /dev/null +++ b/rv64cpu/tb/compliance/CMakeLists.txt @@ -0,0 +1,36 @@ +# ─── Compliance Test CMake ─────────────────────────────────────────────────────── +# +# Builds the compliance test runner and registers riscv-arch-test tests. +# +# ───────────────────────────────────────────────────────────────────────────────── + +# The compliance runner needs the SoC sim binary +# Uncomment when both the SoC and compliance_runner are implemented: +# +# add_verilator_target( +# NAME compliance_runner +# TOP_MODULE richard_soc +# SOURCES ${ALL_RTL_SOURCES} +# INCLUDE_DIRS ${RTL_COMMON_INCLUDES} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/compliance_runner.cpp +# EXTRA_FLAGS --threads 2 +# ) +# +# ─── Register individual compliance tests via CTest ────────────────────────────── +# This is done dynamically by the compliance_runner binary and run_compliance.py. +# You can also manually register tests like: +# +# set(RISCV_ARCH_TEST_DIR ${CMAKE_SOURCE_DIR}/sw/riscv-arch-test) +# +# file(GLOB RV64I_TESTS ${RISCV_ARCH_TEST_DIR}/riscv-test-suite/rv64i_m/I/src/*.S) +# foreach(test_src ${RV64I_TESTS}) +# get_filename_component(test_name ${test_src} NAME_WE) +# add_test( +# NAME compliance_rv64i_${test_name} +# COMMAND compliance_runner --test ${test_src} +# ) +# set_tests_properties(compliance_rv64i_${test_name} PROPERTIES +# LABELS "compliance;rv64i" +# TIMEOUT 30 +# ) +# endforeach() diff --git a/rv64cpu/tb/core/.gitkeep b/rv64cpu/tb/core/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/tb/core/.gitkeep diff --git a/rv64cpu/tb/soc/.gitkeep b/rv64cpu/tb/soc/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/tb/soc/.gitkeep diff --git a/rv64cpu/tb/unit/.gitkeep b/rv64cpu/tb/unit/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/tb/unit/.gitkeep diff --git a/rv64cpu/tools/toolchain-riscv64.cmake b/rv64cpu/tools/toolchain-riscv64.cmake new file mode 100644 index 0000000..c177fda --- /dev/null +++ b/rv64cpu/tools/toolchain-riscv64.cmake @@ -0,0 +1,36 @@ +# ─── RISC-V 64 Bare-Metal Toolchain File ───────────────────────────────────────── +# +# Usage: cmake -B build_sw -DCMAKE_TOOLCHAIN_FILE=tools/toolchain-riscv64.cmake +# + +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR riscv64) + +# ─── Toolchain binaries ───────────────────────────────────────────────────────── +set(CROSS_PREFIX "riscv64-unknown-elf-" CACHE STRING "Cross compiler prefix") + +set(CMAKE_C_COMPILER ${CROSS_PREFIX}gcc) +set(CMAKE_CXX_COMPILER ${CROSS_PREFIX}g++) +set(CMAKE_ASM_COMPILER ${CROSS_PREFIX}gcc) +set(CMAKE_OBJCOPY ${CROSS_PREFIX}objcopy) +set(CMAKE_OBJDUMP ${CROSS_PREFIX}objdump) +set(CMAKE_SIZE ${CROSS_PREFIX}size) + +# ─── Architecture flags ───────────────────────────────────────────────────────── +set(RISCV_ARCH "rv64ima" CACHE STRING "RISC-V ISA string") +set(RISCV_ABI "lp64" CACHE STRING "RISC-V ABI") + +set(CMAKE_C_FLAGS_INIT "-march=${RISCV_ARCH} -mabi=${RISCV_ABI} -nostdlib -ffreestanding -fno-builtin -mcmodel=medany") +set(CMAKE_CXX_FLAGS_INIT "${CMAKE_C_FLAGS_INIT} -fno-exceptions -fno-rtti") +set(CMAKE_ASM_FLAGS_INIT "-march=${RISCV_ARCH} -mabi=${RISCV_ABI}") + +set(CMAKE_EXE_LINKER_FLAGS_INIT "-nostartfiles -static -Wl,--gc-sections") + +# ─── Search paths ─────────────────────────────────────────────────────────────── +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) + +# ─── Disable compiler checks (bare-metal can't run test binaries) ──────────────── +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) diff --git a/rv64cpu/tools/verilator.cmake b/rv64cpu/tools/verilator.cmake new file mode 100644 index 0000000..8c0a006 --- /dev/null +++ b/rv64cpu/tools/verilator.cmake @@ -0,0 +1,60 @@ +# ─── Verilator CMake Helper ────────────────────────────────────────────────────── +# +# Provides the `add_verilator_target()` function to simplify creating +# Verilator simulation executables. +# +# Usage: +# add_verilator_target( +# NAME tb_alu +# TOP_MODULE alu +# SOURCES ${RTL_CORE_DIR}/alu.sv +# INCLUDE_DIRS ${RTL_INCLUDE_DIR} +# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_alu.cpp +# PREFIX Valu +# ) + +function(add_verilator_target) + cmake_parse_arguments(VT + "" # Options + "NAME;TOP_MODULE;PREFIX" # Single-value args + "SOURCES;INCLUDE_DIRS;TB_SOURCES;EXTRA_FLAGS" # Multi-value args + ${ARGN} + ) + + if(NOT VT_PREFIX) + set(VT_PREFIX "V${VT_TOP_MODULE}") + endif() + + # Create C++ executable for the testbench + add_executable(${VT_NAME} ${VT_TB_SOURCES}) + + target_include_directories(${VT_NAME} PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/common + ) + + # Build include dir flags + set(_INCLUDE_FLAGS "") + foreach(_dir ${VT_INCLUDE_DIRS}) + list(APPEND _INCLUDE_FLAGS "-I${_dir}") + endforeach() + + # Verilate the RTL sources + verilate(${VT_NAME} + PREFIX ${VT_PREFIX} + SOURCES ${VT_SOURCES} + TOP_MODULE ${VT_TOP_MODULE} + VERILATOR_ARGS + ${VERILATOR_COMMON_FLAGS} + ${_INCLUDE_FLAGS} + ${VT_EXTRA_FLAGS} + ) + + # Register as CTest + add_test( + NAME ${VT_NAME} + COMMAND ${VT_NAME} + ) + + # Set test timeout + set_tests_properties(${VT_NAME} PROPERTIES TIMEOUT 60) +endfunction() diff --git a/rv64cpu/waves/.gitkeep b/rv64cpu/waves/.gitkeep new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rv64cpu/waves/.gitkeep |