rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[CodeGen] Track reserved register defs precisely	Richard-Qin-X	2026-08-12	3	-12/+33
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*	[CodeGen] Test cloning unnamed functions	Richard-Qin-X	2026-08-12	1	-5/+5
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*	[RISCV] Model dynamic rounding-mode state	Richard-Qin-X	2026-08-12	2	-7/+65
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*	[RISCV] Model FFLAGS accesses	Richard-Qin-X	2026-08-12	5	-7/+129
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*	[MIR] Ignore empty YAML documents	Richard-Qin-X	2026-08-12	2	-16/+64
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*	[RISCV] Describe the GPR select pseudo	Richard-Qin-X	2026-08-12	2	-1/+16
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*	[CodeGen] Accept pointer comparisons in G_ICMP	Richard-Qin-X	2026-08-12	2	-5/+24
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*	[RISCV] Model target-specific generic opcodes	Richard-Qin-X	2026-08-12	2	-1/+164
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*	[RISCV] Support absolute address operand flags	Richard-Qin-X	2026-08-12	8	-15/+97
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*	[MIR] Accept physical-only function live-ins	Richard-Qin-X	2026-08-12	2	-6/+9
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*	[MIR] Accept unnamed stack objects	Richard-Qin-X	2026-08-12	2	-4/+6
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*	[MIR] Accept empty optional register fields	Richard-Qin-X	2026-08-12	3	-9/+20
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*	[CodeGen] Treat reserved registers as always live	Richard-Qin-X	2026-08-11	2	-0/+52
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*	[CodeGen] Accept conservative physical live-ins	Richard-Qin-X	2026-08-11	2	-2/+8
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*	[RISCV] Model typed floating-point register views	Richard-Qin-X	2026-08-11	14	-155/+303
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*	[RISCV] Order call operands like LLVM MIR	Richard-Qin-X	2026-08-11	2	-15/+28
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*	[RISCV] Add LP64 calling-convention facts	Richard-Qin-X	2026-08-11	9	-69/+146
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*	[CodeGen] Remove redundant numeric call-site IDs	Richard-Qin-X	2026-08-11	10	-46/+18
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*	[RISCV] Derive the generated instruction count in tests	Richard-Qin-X	2026-08-11	1	-1/+5
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*	[RISCV] Match LLVM call-frame pseudo semantics	Richard-Qin-X	2026-08-11	6	-85/+80
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*	[RISCV] Use canonical copies for full ABI values	Richard-Qin-X	2026-08-11	2	-7/+15
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*	[RISCV] Lower multiply without M through libcalls	Richard-Qin-X	2026-08-11	2	-3/+182
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*	[RISCV] Accept generic scalars in call lowering	Richard-Qin-X	2026-08-11	2	-3/+18
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*	[RISCV] Honor invocation subtarget features	Richard-Qin-X	2026-08-11	10	-18/+230
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*	[RISCV] Fold narrow binary artifact chains	Richard-Qin-X	2026-08-11	2	-15/+118
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*	[CodeGen] Revisit instructions invalidated by legalization	Richard-Qin-X	2026-08-11	2	-12/+72
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*	[RISCV] Preserve folded constant placement	Richard-Qin-X	2026-08-11	2	-3/+38
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*	[RISCV] Reuse compare operand extensions	Richard-Qin-X	2026-08-11	2	-0/+71
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*	[RISCV] Legalize integer compares to RV64 containers	Richard-Qin-X	2026-08-11	2	-20/+204
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*	[RISCV] Preserve live constants when folding extensions	Richard-Qin-X	2026-08-11	2	-2/+52
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*	[MIR] Omit absent zero-offset MMO bases	Richard-Qin-X	2026-08-11	2	-5/+14
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*	[RISCV] Lower cmpxchg with success	Richard-Qin-X	2026-08-11	2	-1/+131
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*	[RISCV] Preserve narrow cmpxchg results when widening	Richard-Qin-X	2026-08-11	2	-2/+40
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*	[RISCV] Legalize narrow atomic compare exchange	Richard-Qin-X	2026-08-11	3	-2/+228
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*	[MIR] Parse one-ordering compare-exchange MMOs	Richard-Qin-X	2026-08-11	4	-52/+94
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	18	-65/+3013
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*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	53	-650/+2429
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	90	-2995/+11345
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	52	-58/+7361
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	52	-3/+5886
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	91	-40/+14212
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	29	-9/+4264
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	70	-194/+7008
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*	[CodeGen] Implement machine liveness analysis	Richard-Qin-X	2026-08-09	15	-53/+3294
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	22	-56/+3594
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	11	-0/+5793
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	25	-0/+10628
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	11	-87/+5460
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	19	-9/+2062
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[MIR] Complete document parsing and printing	Richard-Qin-X	2026-08-07	45	-218/+11465
\| \| \| \|	Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.