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| * feat(tlb): add parameterized L1 TLB module and corresponding unit testsRichard Qin2026-04-013-0/+805
| * docs: update README and ISA support matrix with new dependencies and complian...Richard Qin2026-04-012-17/+50
| * feat(compliance): implement ACT4 strict compliance flow with ELF runnerRichard Qin2026-04-014-72/+756
| * feat: Add riscv-arch-test submodule for RISC-V architecture testingRichard Qin2026-04-012-0/+3
| * Merge pull request #5 from Richard-Qin-001/testing-improvement-store-page-fau...Richard Qin2026-04-011-2/+10
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| | * test(trap_ctrl): add store page fault unit test caseRichard Qin2026-03-311-2/+10
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| * feat: Complete CSR/privileged/exception interrupt path and fill in strict acc...Richard Qin2026-04-0119-201/+1269
| * Trap Control unit and testsRichard Qin2026-03-193-0/+406
| * Update the latest progressRichard Qin2026-03-191-3/+11
| * CSR unit and testsRichard Qin2026-03-195-10/+893
| * M/S/U Mode csr pakageRichard Qin2026-03-181-0/+110
| * Add fibonacci tests and fix bugsRichard Qin2026-03-183-8/+77
| * fixed vm_trace bugRichard Qin2026-03-181-6/+6
| * CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-185-8/+1252
| * Hazard unit and testsRichard Qin2026-03-183-0/+446
| * Merge pull request #3 from Richard-Qin-001/fix/wb-stage-review-99385726772028...Richard Qin2026-03-182-17/+25
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| | * test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
| | * refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
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| * Write Back stage unit and testsRichard Qin2026-03-183-0/+240
| * Merge pull request #2 from Richard-Qin-001/audit-report-fixes-180556562870443...Richard Qin2026-03-186-29/+29
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| | * Merge branch 'main' into audit-report-fixes-18055656287044378367Richard Qin2026-03-180-0/+0
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| * | Memory Stage and MEM/WB pipeline stage registerRichard Qin2026-03-185-0/+739
| * | fix known bugsRichard Qin2026-03-176-21/+68
| * | EX/MEM Pipeline Register unit and testsRichard Qin2026-03-177-2/+386
| | * docs: Finalized Richard CPU RTL architectural and naming convention audit rep...Richard Qin2026-03-1713-20/+1190
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| * Execute Stage unit and testsRichard Qin2026-03-173-0/+343
| * ID/EX Pipeline Register and testsRichard Qin2026-03-173-0/+354
| * IF/ID RegFile and testsRichard Qin2026-03-173-0/+193
| * Instruction Decoder Stage unit and testsRichard Qin2026-03-173-0/+345
| * Instruction fetching stage unit and testRichard Qin2026-03-163-0/+180
| * branch unit and testRichard Qin2026-03-164-0/+174
| * Merge pull request #1 from Richard-Qin-001/expand-testsRichard Qin2026-03-163-21/+143
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| | * format outputRichard Qin2026-03-163-13/+20
| | * expand tests and format outputRichard Qin2026-03-163-9/+124
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| * fix naming problemsRichard Qin2026-03-167-84/+77
| * Naming conventionRichard Qin2026-03-161-0/+159
| * Decoder unit and testRichard Qin2026-03-163-9/+697
| * Register file unit and testRichard Qin2026-03-163-13/+172
| * LicenseRichard Qin2026-03-151-0/+17
| * Add and test alu unitRichard Qin2026-03-156-8/+241
| * initial commit: project architectureRichard Qin2026-03-1541-0/+2185
* [libbase][adt] Add ilistRichard Qin4 days1-0/+546
* [libbase][adt] Add simple ilistRichard Qin4 days1-0/+482
* [libbase][adt] Add ilist baseRichard Qin4 days1-0/+139
* [libbase][adt] Add ilist iteratorRichard Qin4 days1-0/+591
* [libbase][adt] Add ilist nodeRichard Qin4 days1-0/+470
* [libbase][adt] Add ilist node baseRichard Qin4 days1-0/+167
* [libbase][adt] Add ilist node optionsRichard Qin4 days1-0/+244
* [libbase][adt] Add pointer utility typesRichard Qin5 days2-0/+466
* [libbase] Format C++ CodeRichard Qin6 days6-315/+534
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 21:02:19 +0000