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* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-123-55/+15
* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-122-6/+8
* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-122-2/+29
* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-122-0/+54
* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-124-38/+288
* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-122-15/+47
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-125-3/+200
* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-122-5/+6
* [MIR] Create virtual registers referenced by live-insRichard-Qin-X2026-08-124-6/+57
* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-123-12/+33
* [CodeGen] Test cloning unnamed functionsRichard-Qin-X2026-08-121-5/+5
* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-122-7/+65
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-125-7/+129
* [MIR] Ignore empty YAML documentsRichard-Qin-X2026-08-122-16/+64
* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-122-1/+16
* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-122-5/+24
* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-122-1/+164
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-128-15/+97
* [MIR] Accept physical-only function live-insRichard-Qin-X2026-08-122-6/+9
* [MIR] Accept unnamed stack objectsRichard-Qin-X2026-08-122-4/+6
* [MIR] Accept empty optional register fieldsRichard-Qin-X2026-08-123-9/+20
* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-112-0/+52
* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-112-2/+8
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-1114-155/+303
* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-112-15/+28
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-119-69/+146
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-1110-46/+18
* [RISCV] Derive the generated instruction count in testsRichard-Qin-X2026-08-111-1/+5
* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-116-85/+80
* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-112-7/+15
* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-112-3/+182
* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-112-3/+18
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-1110-18/+230
* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-112-15/+118
* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-112-12/+72
* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-112-3/+38
* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-112-0/+71
* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-112-20/+204
* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-112-2/+52
* [MIR] Omit absent zero-offset MMO basesRichard-Qin-X2026-08-112-5/+14
* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-112-1/+131
* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-112-2/+40
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-113-2/+228
* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-114-52/+94
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-1118-65/+3013
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-1153-650/+2429
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1090-2995/+11345
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-0952-58/+7361
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0952-3/+5886
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0991-40/+14212
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