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| * checkpoint: preserve current RV64 CPU development stateRichard Qin4 days38-911/+7735
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| * refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-074-36/+36
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| * refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-079-90/+135
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| * feat(tlb): enhance TLB functionality with ASID-targeted flush and additional ↵Richard Qin2026-04-073-1/+70
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| * feat(tlb): add parameterized L1 TLB module and corresponding unit testsRichard Qin2026-04-013-0/+805
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| * docs: update README and ISA support matrix with new dependencies and ↵Richard Qin2026-04-012-17/+50
| | | | | | | | compliance status
| * feat(compliance): implement ACT4 strict compliance flow with ELF runnerRichard Qin2026-04-014-72/+756
| | | | | | | | add functional compliance_runner with ELF loading, memory model, symbol-based signature dump, and tohost handling; wire compliance subdir/target in CMake; upgrade run_compliance.py for ACT4 suite mapping, robust binary/reference discovery, strict signature comparison, and aggregate suites (rv64g/rv64full).
| * feat: Add riscv-arch-test submodule for RISC-V architecture testingRichard Qin2026-04-012-0/+3
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| * Merge pull request #5 from ↵Richard Qin2026-04-011-2/+10
| |\ | | | | | | | | | | | | Richard-Qin-001/testing-improvement-store-page-fault-17466277746563964545 🧪 [trap_ctrl] add store page fault test case
| | * test(trap_ctrl): add store page fault unit test caseRichard Qin2026-03-311-2/+10
| |/ | | | | | | | | | | | | | | | | Added a specific test scenario for Store Page Fault in tb/unit/tb_trap_ctrl.cc. - Defined EXC_STORE_PAGE_FAULT (15) constant. - Implemented a test case that asserts trap_store_page_fault and verifies mcause and mtval. - Improved clarity by renaming existing page fault test labels to LoadPageFault. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
| * feat: Complete CSR/privileged/exception interrupt path and fill in strict ↵Richard Qin2026-04-0119-201/+1269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | acceptance tests - Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process - Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return - Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios - Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers - Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case - Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc. - Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite Verification: - Build passed - Full CTest passed (22/22)
| * Trap Control unit and testsRichard Qin2026-03-193-0/+406
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| * Update the latest progressRichard Qin2026-03-191-3/+11
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| * CSR unit and testsRichard Qin2026-03-195-10/+893
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| * M/S/U Mode csr pakageRichard Qin2026-03-181-0/+110
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| * Add fibonacci tests and fix bugsRichard Qin2026-03-183-8/+77
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| * fixed vm_trace bugRichard Qin2026-03-181-6/+6
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| * CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-185-8/+1252
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| * Hazard unit and testsRichard Qin2026-03-183-0/+446
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| * Merge pull request #3 from ↵Richard Qin2026-03-182-17/+25
| |\ | | | | | | | | | | | | Richard-Qin-001/fix/wb-stage-review-9938572677202897816 Refactor WB Stage for Timing, and Precise Exceptions
| | * test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Renamed `wb_reg_write_data` to `wb_rd_wdata` in all assertions to match the updated module ports. - Renamed `wb_reg_write_addr` to `wb_rd_addr` in all assertions. - Initialized the new `mem_wb_pc_plus_4` input in the testbench setup to correctly test the JAL/JALR datapath. - Added assertions to explicitly test that `wb_reg_write_en` and `csr_req` are gated when an exception occurs. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
| | * refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
| |/ | | | | | | | | | | | | | | - Renamed `wb_reg_write_data` and `wb_reg_write_addr` to `wb_rd_wdata` and `wb_rd_addr` respectively to comply with `docs/naming_convention.md`. - Removed the 64-bit adder for `mem_wb_pc + 64'd4` from the WB stage to improve timing. Introduced a new `mem_wb_pc_plus_4` pipeline input instead. - Added a `has_trap` signal to gate architectural state updates (`wb_reg_write_en` and `csr_req`) upon exceptions, ensuring precise exceptions without corrupting the register file or CSRs. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
| * Write Back stage unit and testsRichard Qin2026-03-183-0/+240
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| * Merge pull request #2 from ↵Richard Qin2026-03-186-29/+29
| |\ | | | | | | | | | | | | Richard-Qin-001/audit-report-fixes-18055656287044378367 Finalized Richard CPU RTL Audit Report
| | * Merge branch 'main' into audit-report-fixes-18055656287044378367Richard Qin2026-03-180-0/+0
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| * | Memory Stage and MEM/WB pipeline stage registerRichard Qin2026-03-185-0/+739
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| * | fix known bugsRichard Qin2026-03-176-21/+68
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| * | EX/MEM Pipeline Register unit and testsRichard Qin2026-03-177-2/+386
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| | * docs: Finalized Richard CPU RTL architectural and naming convention audit ↵Richard Qin2026-03-1713-20/+1190
| |/ | | | | | | | | | | | | | | report. No source code changes were made; this branch serves as the finalized state for the provided audit. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
| * Execute Stage unit and testsRichard Qin2026-03-173-0/+343
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| * ID/EX Pipeline Register and testsRichard Qin2026-03-173-0/+354
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| * IF/ID RegFile and testsRichard Qin2026-03-173-0/+193
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| * Instruction Decoder Stage unit and testsRichard Qin2026-03-173-0/+345
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| * Instruction fetching stage unit and testRichard Qin2026-03-163-0/+180
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| * branch unit and testRichard Qin2026-03-164-0/+174
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| * Merge pull request #1 from Richard-Qin-001/expand-testsRichard Qin2026-03-163-21/+143
| |\ | | | | | | Expand tests and format output
| | * format outputRichard Qin2026-03-163-13/+20
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| | * expand tests and format outputRichard Qin2026-03-163-9/+124
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| * fix naming problemsRichard Qin2026-03-167-84/+77
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| * Naming conventionRichard Qin2026-03-161-0/+159
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| * Decoder unit and testRichard Qin2026-03-163-9/+697
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| * Register file unit and testRichard Qin2026-03-163-13/+172
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| * LicenseRichard Qin2026-03-151-0/+17
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| * Add and test alu unitRichard Qin2026-03-156-8/+241
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| * initial commit: project architectureRichard Qin2026-03-1541-0/+2185
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* [libbase][adt] Add ilistRichard Qin5 days1-0/+546
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* [libbase][adt] Add simple ilistRichard Qin5 days1-0/+482
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* [libbase][adt] Add ilist baseRichard Qin5 days1-0/+139
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* [libbase][adt] Add ilist iteratorRichard Qin5 days1-0/+591
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* [libbase][adt] Add ilist nodeRichard Qin5 days1-0/+470
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