rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[CodeGen] Implement RISC-V finalize-isel	Richard-Qin-X	2026-08-26	1	-0/+1
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*	[CodeGen] Remove unsupported pre-PEI pseudo expansion	Richard-Qin-X	2026-08-19	1	-1/+0
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*	[RISCV][GlobalISel] Select and expand global addresses	Richard-Qin-X	2026-08-19	1	-0/+1
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*	[CodeGen] Match LLVM Legalizer ownership	Richard-Qin-X	2026-08-14	1	-0/+4
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*	[CodeGen] Unify scalar low-level types	Richard-Qin-X	2026-08-13	1	-8/+10
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*	[CodeGen] Match LLVM branch relaxation semantics	Richard-Qin-X	2026-08-13	1	-0/+1
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	1	-0/+1
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	1	-0/+1
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	1	-0/+49
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*	[MIR] Complete document parsing and printing	Richard-Qin-X	2026-08-07	1	-0/+1
\| \| \| \|	Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
*	[CodeGen] Add transactional MachineIR builder	Richard-Qin-X	2026-08-01	1	-0/+26
\| \| \| \|	Validate insertion cursors, operand ownership, descriptor constraints, ties, implicit registers, and memory operands before allocating or publishing an instruction. Share instruction legality checks with the verifier path and preserve deterministic insertion order.
*	[CodeGen] Add machine instruction descriptors	Richard-Qin-X	2026-08-01	1	-0/+264
	Introduce an immutable instruction registry with exact operand, implicit register, tie, pseudo lifecycle, and memory constraints. Validate descriptor tables before publication and use the same rules to verify MachineInstr instances.