aboutsummaryrefslogtreecommitdiff
path: root/backend/include/rcc/CodeGen/InstructionDescriptor.h
Commit message (Collapse)AuthorAgeFilesLines
* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-131-8/+10
|
* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-131-0/+1
|
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-0/+1
|
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-0/+1
|
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-0/+49
|
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-071-0/+1
| | | | Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
* [CodeGen] Add transactional MachineIR builderRichard-Qin-X2026-08-011-0/+26
| | | | Validate insertion cursors, operand ownership, descriptor constraints, ties, implicit registers, and memory operands before allocating or publishing an instruction. Share instruction legality checks with the verifier path and preserve deterministic insertion order.
* [CodeGen] Add machine instruction descriptorsRichard-Qin-X2026-08-011-0/+264
Introduce an immutable instruction registry with exact operand, implicit register, tie, pseudo lifecycle, and memory constraints. Validate descriptor tables before publication and use the same rules to verify MachineInstr instances.