| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Complete LaneMask bitwise operations | Richard-Qin-X | 2026-08-28 | 1 | -0/+14 |
| * | [MIR] Normalize explicit successor probabilities | Richard-Qin-X | 2026-08-14 | 1 | -0/+3 |
| * | [RISCV] Legalize llvm.va_copy | Richard-Qin-X | 2026-08-12 | 1 | -0/+9 |
| * | [MIR] Accept fixed-baseline LLVM syntax | Richard-Qin-X | 2026-08-11 | 1 | -1/+1 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -0/+4 |
| * | [CodeGen] Complete machine pass and ABI lowering infrastructure | Richard-Qin-X | 2026-08-07 | 1 | -0/+3 |
| * | [CodeGen] Model complete MIR operands | Richard-Qin-X | 2026-08-03 | 1 | -0/+4 |
| * | [CodeGen] Add MIR function and block attributes | Richard-Qin-X | 2026-08-01 | 1 | -0/+25 |
| * | [CodeGen] Add target register descriptions | Richard-Qin-X | 2026-08-01 | 1 | -0/+2 |
| * | [CodeGen] Add constant and jump table state | Richard-Qin-X | 2026-08-01 | 1 | -0/+6 |
| * | [CodeGen] Add machine instruction descriptors | Richard-Qin-X | 2026-08-01 | 1 | -0/+10 |
| * | [CodeGen] Add machine IR value semantics | Richard-Qin-X | 2026-08-01 | 1 | -0/+274 |
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