rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	1	-0/+1
\|
*	[MIR] Complete document parsing and printing	Richard-Qin-X	2026-08-07	1	-0/+3
\| \| \| \|	Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
*	[CodeGen] Model complete MIR operands	Richard-Qin-X	2026-08-03	1	-4/+174
\|
*	[CodeGen] Model machine debug metadata	Richard-Qin-X	2026-08-02	1	-2/+3
\| \| \| \|	Replace marker-based metadata operands with scoped references and inline DIExpression values. Add structured DILocation chains, instruction debug attachments, stack variable records, and entry values with unified verification, builder support, and deterministic cloning.
*	[CodeGen] Add machine instruction descriptors	Richard-Qin-X	2026-08-01	1	-0/+1
\| \| \| \|	Introduce an immutable instruction registry with exact operand, implicit register, tie, pseudo lifecycle, and memory constraints. Validate descriptor tables before publication and use the same rules to verify MachineInstr instances.
*	[CodeGen] Build the core MachineIR object model	Richard-Qin-X	2026-08-01	1	-0/+344
	Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references. Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.