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* [GlobalISel] Lower integer rotate operationsRichard-Qin-X2026-08-151-0/+1
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* [GlobalISel] Preserve worklists when moving CSE instructionsRichard-Qin-X2026-08-151-0/+3
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* [GlobalISel] Lower three-way integer comparisonsRichard-Qin-X2026-08-151-0/+1
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* [GlobalISel] Lower integer min/max operationsRichard-Qin-X2026-08-151-0/+1
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* [GlobalISel] Legalize scalar pointer castsRichard-Qin-X2026-08-151-0/+3
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* [GlobalISel] Narrow scalar shiftsRichard-Qin-X2026-08-151-0/+30
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* [GlobalISel] Narrow scalar selectsRichard-Qin-X2026-08-151-0/+2
| | | | Match LLVM's narrowScalarSelect lowering for wide scalar values. Build widened sources from LLT destinations so CSE hits reuse the actual result register instead of introducing copies.
* [GlobalISel] Narrow scalar bitwise operationsRichard-Qin-X2026-08-151-0/+2
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* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-1510-62/+320
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* [GlobalISel] Legalize G_ABDS and G_ABDURichard-Qin-X2026-08-142-0/+6
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* [GlobalISel] Legalize G_ABSRichard-Qin-X2026-08-145-21/+32
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* [RISCV] Legalize va_copy intrinsicsRichard-Qin-X2026-08-141-43/+36
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* [MIR] Normalize explicit successor probabilitiesRichard-Qin-X2026-08-141-0/+3
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* [GlobalISel] Match LLVM legalization value trackingRichard-Qin-X2026-08-147-426/+525
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* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-1412-8/+2328
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* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-135-77/+55
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* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-134-11/+28
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* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-131-0/+1
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* [RISCV] Match LLVM register bank mappingsRichard-Qin-X2026-08-132-5/+18
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* [MIR] Omit predictable successors in simplified outputRichard-Qin-X2026-08-131-0/+7
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* [CodeGen] Remove duplicate analysis declarationsRichard-Qin-X2026-08-132-5/+0
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* [CodeGen] Remove the unused property queryRichard-Qin-X2026-08-131-1/+0
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* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-135-181/+5
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* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-135-118/+23
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* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-134-0/+426
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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1337-822/+380
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* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-139-416/+542
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* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-133-49/+62
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-8/+4
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* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-128-163/+222
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* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-125-51/+31
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* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-129-28/+28
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* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-121-0/+72
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* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-121-0/+1
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* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-121-1/+0
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* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+9
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* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-6/+0
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* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-1/+6
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* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-116-3/+330
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* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1010-25/+136
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* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-095-0/+403
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* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0936-0/+1501
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* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-096-0/+174
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* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0917-16/+1154
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* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-093-0/+414
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* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-086-4/+94
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* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+157
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* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-077-0/+1720
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* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-0/+49
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* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+7
| | | | Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 10:04:04 +0000