rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[GlobalISel] Preserve worklists when moving CSE instructions	Richard-Qin-X	2026-08-15	1	-0/+3
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*	[GlobalISel] Lower three-way integer comparisons	Richard-Qin-X	2026-08-15	1	-0/+1
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*	[GlobalISel] Lower integer min/max operations	Richard-Qin-X	2026-08-15	1	-0/+1
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*	[GlobalISel] Legalize scalar pointer casts	Richard-Qin-X	2026-08-15	1	-0/+3
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*	[GlobalISel] Narrow scalar shifts	Richard-Qin-X	2026-08-15	1	-0/+30
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*	[GlobalISel] Narrow scalar selects	Richard-Qin-X	2026-08-15	1	-0/+2
\| \| \| \|	Match LLVM's narrowScalarSelect lowering for wide scalar values. Build widened sources from LLT destinations so CSE hits reuse the actual result register instead of introducing copies.
*	[GlobalISel] Narrow scalar bitwise operations	Richard-Qin-X	2026-08-15	1	-0/+2
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*	[GlobalISel] Match LLVM CSE builder result semantics	Richard-Qin-X	2026-08-15	10	-62/+320
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*	[GlobalISel] Legalize G_ABDS and G_ABDU	Richard-Qin-X	2026-08-14	2	-0/+6
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*	[GlobalISel] Legalize G_ABS	Richard-Qin-X	2026-08-14	5	-21/+32
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*	[RISCV] Legalize va_copy intrinsics	Richard-Qin-X	2026-08-14	1	-43/+36
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*	[MIR] Normalize explicit successor probabilities	Richard-Qin-X	2026-08-14	1	-0/+3
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*	[GlobalISel] Match LLVM legalization value tracking	Richard-Qin-X	2026-08-14	7	-426/+525
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*	[CodeGen] Match LLVM Legalizer ownership	Richard-Qin-X	2026-08-14	12	-8/+2328
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*	[CodeGen] Unify scalar low-level types	Richard-Qin-X	2026-08-13	5	-77/+55
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*	[CodeGen] Match LLVM machine copy propagation	Richard-Qin-X	2026-08-13	4	-11/+28
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*	[CodeGen] Match LLVM branch relaxation semantics	Richard-Qin-X	2026-08-13	1	-0/+1
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*	[RISCV] Match LLVM register bank mappings	Richard-Qin-X	2026-08-13	2	-5/+18
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*	[MIR] Omit predictable successors in simplified output	Richard-Qin-X	2026-08-13	1	-0/+7
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*	[CodeGen] Remove duplicate analysis declarations	Richard-Qin-X	2026-08-13	2	-5/+0
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*	[CodeGen] Remove the unused property query	Richard-Qin-X	2026-08-13	1	-1/+0
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*	[IR] Split LL parsing, assembly writing, and data layout	Richard-Qin-X	2026-08-13	5	-181/+5
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*	[Support] Split APInt and APFloat ownership	Richard-Qin-X	2026-08-13	5	-118/+23
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*	[CodeGen] Align MIR parser and printer ownership	Richard-Qin-X	2026-08-13	4	-0/+426
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*	[CodeGen] Align pass manager ownership	Richard-Qin-X	2026-08-13	37	-822/+380
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*	[CodeGen] Split machine liveness components	Richard-Qin-X	2026-08-13	9	-416/+542
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*	[CodeGen] Split PHI elimination and two-address rewriting	Richard-Qin-X	2026-08-13	3	-49/+62
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*	[RISCV] Split the GlobalISel target components	Richard-Qin-X	2026-08-12	1	-8/+4
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*	[GlobalISel] Split the generic pipeline components	Richard-Qin-X	2026-08-12	8	-163/+222
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*	[RISCV] Consolidate instruction behavior in RISCVInstrInfo	Richard-Qin-X	2026-08-12	5	-51/+31
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*	[CodeGen] Add TargetInstrInfo ownership	Richard-Qin-X	2026-08-12	9	-28/+28
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*	[Tooling] Complete the LLVM MIR command-line contract	Richard-Qin-X	2026-08-12	1	-0/+72
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*	[Tooling] Adopt LLVM MIR command-line spellings	Richard-Qin-X	2026-08-12	1	-0/+1
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*	[MIR] Remove alternate layout and float APIs	Richard-Qin-X	2026-08-12	1	-1/+0
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*	[RISCV] Legalize llvm.va_copy	Richard-Qin-X	2026-08-12	1	-0/+9
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*	[CodeGen] Remove redundant numeric call-site IDs	Richard-Qin-X	2026-08-11	1	-6/+0
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*	[RISCV] Honor invocation subtarget features	Richard-Qin-X	2026-08-11	1	-1/+6
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*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	6	-3/+330
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	10	-25/+136
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	5	-0/+403
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	36	-0/+1501
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	6	-0/+174
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	17	-16/+1154
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*	[CodeGen] Implement machine liveness analysis	Richard-Qin-X	2026-08-09	3	-0/+414
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	6	-4/+94
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	2	-0/+157
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	7	-0/+1720
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	1	-0/+49
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	1	-0/+7
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[MIR] Complete document parsing and printing	Richard-Qin-X	2026-08-07	9	-22/+351
\| \| \| \|	Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.