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Commit message (Collapse)AuthorAgeFilesLines
* [CodeGen] Separate assembly emission ownershipRichard-Qin-X2026-08-283-42/+78
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* [CodeGen] Separate pass instrumentation ownershipRichard-Qin-X2026-08-282-1/+154
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* [CodeGen] Centralize machine instruction erasureRichard-Qin-X2026-08-282-1/+3
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* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-271-0/+1
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* [GlobalISel] Select each instruction onceRichard-Qin-X2026-08-271-6/+0
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* [CodeGen] Run machine optimizations onceRichard-Qin-X2026-08-272-2/+4
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* [CodeGen] Run scheduling transformations onceRichard-Qin-X2026-08-262-2/+3
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* [CodeGen] Remove transactional register allocationRichard-Qin-X2026-08-261-5/+5
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* [CodeGen] Run SSA exit transformations onceRichard-Qin-X2026-08-262-2/+4
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* [GlobalISel] Run machine transformations onceRichard-Qin-X2026-08-263-3/+6
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* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-261-4/+6
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* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-262-0/+38
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* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-262-0/+65
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* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-252-5/+16
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* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-251-0/+1
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* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-251-0/+97
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* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-242-0/+35
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* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-243-5/+15
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* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-242-46/+6
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* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-242-0/+35
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* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-222-0/+18
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* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-227-7/+96
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* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-191-27/+0
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* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-192-39/+1
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* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-191-1/+0
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* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-193-16/+0
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* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-192-0/+65
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* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-196-1/+31
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* [RISCV][GlobalISel] Generate integer load selectionRichard-Qin-X2026-08-191-0/+1
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* [RISCV][GlobalISel] Match floating comparisonsRichard-Qin-X2026-08-191-0/+1
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* [RISCV][GlobalISel] Generate conditional branch selectionRichard-Qin-X2026-08-171-0/+1
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* [RISCV][GlobalISel] Generate integer extension selectionsRichard-Qin-X2026-08-171-0/+6
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* [RISCV][GlobalISel] Generate shift selectionsRichard-Qin-X2026-08-162-3/+28
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* [RISCV][GlobalISel] Generate integer comparisonsRichard-Qin-X2026-08-162-2/+32
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* [RISCV][GlobalISel] Select comparisons against zeroRichard-Qin-X2026-08-161-0/+5
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* tablegen: Generate GlobalISel match tablesRichard-Qin-X2026-08-162-2/+72
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* [GlobalISel] Propagate no-fp-except flagsRichard-Qin-X2026-08-161-0/+10
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* [GlobalISel] Lower inline memory copiesRichard-Qin-X2026-08-151-0/+1
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* [GlobalISel] Legalize scalar memory operationsRichard-Qin-X2026-08-151-0/+6
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* [GlobalISel] Legalize saturating arithmeticRichard-Qin-X2026-08-151-0/+3
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* [GlobalISel] Legalize multiply with overflowRichard-Qin-X2026-08-151-0/+3
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* [GlobalISel] Legalize multi-precision multiplicationRichard-Qin-X2026-08-151-0/+7
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* [GlobalISel] Lower funnel shiftsRichard-Qin-X2026-08-151-0/+1
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* [RISCV][GlobalISel] Legalize floating-point remainderRichard-Qin-X2026-08-154-6/+20
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* [GlobalISel] Lower stack operationsRichard-Qin-X2026-08-152-5/+30
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* [GlobalISel] Legalize scalar PHI operationsRichard-Qin-X2026-08-151-0/+2
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* [RISCV][GlobalISel] Legalize scalar bit count operationsRichard-Qin-X2026-08-152-0/+3
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* [GlobalISel] Lower byte-swap operationsRichard-Qin-X2026-08-151-0/+1
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* [GlobalISel] Lower combined division and remainderRichard-Qin-X2026-08-151-0/+1
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* [GlobalISel] Lower integer operations to libcallsRichard-Qin-X2026-08-153-7/+22
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